Amplifiers – With periodic switching input-output
Reexamination Certificate
2000-06-08
2002-04-30
Mottola, Steven J. (Department: 2817)
Amplifiers
With periodic switching input-output
C330S255000
Reexamination Certificate
active
06380801
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
This invention relates generally to operational amplifiers and more particularly to operational amplifiers, which include chop circuits to remove offset voltages and low frequency (1/f) noise.
As is known in the art, operational amplifiers have a wide range of applications. Some operational amplifiers use chop circuits to remove offset voltages and low frequency noise. Further, as is known, some applications require that the operational amplifier operate with its inputs very close to, or even beyond, both voltage supplies of the amplifier—such an amplifier is described as having a rail-to-rail input range. Some operational amplifiers use Complementary Metal Oxide Semiconductor (CMOS) transistors. More particularly, such an amplifier may have a differential input pair of MOS transistors. For example, if it is a PMOS pair, then the input voltage can be at, or below, ground potential and the amplifier will continue to function properly. This operational amplifier also has a PMOS transistor providing the tail current to the differential input pair of transistors. However, if the input voltage moves upwards towards the positive supply voltage (i.e., the positive supply rail), then there is eventually not enough drain-to-source-voltage across the PMOS transistor to provide the tail current to the input pair of transistors and thus the amplifier ceases to operate properly.
One technique to solve this problem, and thereby provide an amplifier with rail-to-rail input range, is by using two differential input pairs of MOS transistors, the transistors in one of the pairs being complementary in type to the transistors in the other pair. The technique has been applied to bipolar operational amplifiers as well as to MOS operational amplifiers. In the case of bipolar operational amplifiers, one of the pairs uses NPN transistors and the other uses PNP transistors. In the case of MOS operational amplifiers, one of the pairs uses NMOS transistors and the other uses PMOS transistors.
More particularly, referring to
FIG. 1
, a MOS operational amplifier
10
is shown to include two differential input stages,
12
and
14
. PMOS stage
12
includes an input differential pair of PMOS transistors PMOS
1
, PMOS
2
. NMOS stage
14
includes a second input differential pair of NMOS transistors NMOS
1
, NMOS
2
. The amplifier
10
is coupled to a supply voltage via upper voltage rail
11
and lower rail
13
. The potential on the upper voltage rail
11
is AHI, here 5 volts, and the potential on the lower voltage rail
13
is here ground potential. The basic idea is to provide for the lower part of the input voltage range with the PMOS stage
12
and the upper part of the input voltage range with the NMOS stage
14
.
The operational amplifier
10
is fed by a non-inverting input signal, applied to a non-inverting input terminal IN+, and by an inverting input signal, applied to an inverting input terminal IN−. The difference between these two signals is the differential input signal. An input chop circuit
16
is coupled between the input terminals IN+ and IN− and the gates of the transistors PMOS
1
, PMOS
2
and NMOS
1
, NMOS
2
, as shown. Thus in one state (i.e., CHOP=0), the input chop circuit
16
couples the IN+ input terminal to the gates of transistors NMOS
1
and PMOS
1
and the IN− input terminal to the gates of transistors NMOS
2
and PMOS
2
. In the other state (i.e., CHOP=1), the input chop circuit
16
couples the IN+ input terminal to the gates of transistors NMOS
2
and PMOS
2
and the IN− input terminal to the gates of transistors NMOS
1
and PMOS
1
. The currents from the two differential stages
12
,
14
are combined, in this example, in a folded cascode stage
20
. The output of the folded cascode section
20
is coupled to an output or second section
22
(which includes a common mode stabilization section
24
) through an output chop circuit
26
. The function of the chop circuits
16
and
26
is, as noted above, to remove offset voltages and low frequency noise of the input stages
12
and
14
.
PMOS
3
, PMOS
4
form the tail current source in stage
12
and NMOS
3
, NMOS
4
form the tail current source in stage
14
. A differential input stage is said to be fully operational if the applied non-inverting and inverting input signals ensure sufficient gate-source voltage for the transistors in the differential input pair and sufficient drain-source voltages for the transistors that comprise the tail current source. The tail current is substantially invariant with input signal. A differential input stage is said to be partially operational if the applied non-inverting and inverting input signals don't ensure sufficient gate-source voltage for the transistors in the differential input pair and sufficient drain-source voltages for the transistors that comprise the tail current source. The tail current varies substantially with input signal. A differential input stage is said to be non-operational if the applied non-inverting and inverting input signals are insufficient to cause any current to flow in the input stage.
While chopper stabilization works well in operational amplifiers having a single differential input pair, we have determined that problems arise in chopping the operational amplifier having two differential input pairs such as that in FIG.
1
. For example, let is be assumed that the NMOS input pair NMOS
1
, NMOS
2
are well matched but that there is a 5 millivolt difference between the threshold voltage (V
T
) of the PMOS input pair PMOS
1
, PMOS
2
. Furthermore, the operational amplifier
10
(
FIG. 1
) is configured as a voltage follower with it's output OUT connected to the inverting input terminal IN−. The signal VIN is applied to the non-inverting input terminal IN+ of the operational amplifier
10
as the non-inverting input signal. Referring to
FIG. 2
, VIN is swept rail-to-rail, in this case, from near 0 volts to near AHI, here +5 volts. As noted above, there are two configurations for the chop circuits (i.e., CHOP=0 and CHOP=1). The error voltage between the operational amplifier
10
output voltage and VIN, as VIN is swept, is shown for the condition when the chop circuits are in state CHOP=0 and in state CHOP=1. The upper graph shows the error for CHOP=0. It is noted that the error starts in region
30
at 5 millivolts because stage
12
is fully operational and stage
14
is non-operational and, as assumed above, the transistors PMOS
1
and PMOS
2
have a 5 millivolt differential in the transistor's threshold voltage V
T
. Near AHI, in region
32
, above 4.5 volts, with stage
14
fully operational and stage
12
non-operational, the error is 0 millivolts, because of perfect matching of NMOS
1
and NMOS
2
. In the intervening region
34
where both differential input stages
12
and
14
are fully operational, the error is approximately halfway between 0 millivolts and 5 millivolts. The middle chart shows the error for the CHOP=1 condition. In this case, the error is −5 millivolts in region
30
because the pair of transistors PMOS
1
and PMOS
2
(which have the 5 millivolts differential in V
T
) is chopped and the error is still zero volts error in region
32
where the perfectly matched NMOS
1
and NMOS
2
transistors are chopped. It is approximately −2.5 millivolts in region
34
.
The net error (which should theoretically be zero from averaging the two chop states, CHOP=0 and CHOP=1) is shown in the lower graph in FIG.
2
. Note that the units in net error (along the Y-axis) are now in microvolts rather than in millivolts. Chopping can be seen to operate well in three regions: in region
30
where stage
12
is fully operational and stage
14
is non-operational (i.e., below 0.5 volts); in region
32
where stage
14
is fully operational and stage
12
is non-operational (i.e., above 4.5 volts); and in region
34
where both stages
12
and
14
are filly opera
Analog Devices Inc.
Mottola Steven J.
Samuels , Gauthier & Stevens, LLP
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