Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-02-23
2002-03-12
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S149000, C365S154000, C365S185200, C365S185230, C365S189070
Reexamination Certificate
active
06356503
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to memory compilers for semiconductor memories having a circuit for reducing clock-to-wordline time delay.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that performance parameters such as access time, overall memory cycle time, etc. play a pivotal role in designing a memory circuit, whether provided in an embedded SOC application or as a stand-alone device. For high speed memories, the time between the initiation of the random access (signified by the leading edge of the clock signal in synchronous memories) and the selection of the wordline (i.e., the access port of the storage bit cell, e.g., a Static Random Access Memory (SRAM) cell) is part of the critical path of the overall access time (i.e., latency). Clearly, for minimum latency, the delay of this path must be reduced as much as possible.
Further, in several applications, the memory cycle time—typically defined as the reciprocal of time rate at which address signals are changed while reading or writing at random memory cells—needs to be minimized also. That is, the de-selection of the wordline must also be relatively fast, as the pre-charge operation of the bitlines at the end of the cycle cannot happen until the wordline has been de-selected. Otherwise, the pre-charge operation has to contend with the charged condition of the wordline (and the memory cells selected by the wordline) and, accordingly, bitline equalization will be negatively impacted.
It should be apparent to those skilled in the art that the dual requirement of fast selection and fast de-selection phases of the cycle time typically compromises the performance of both in the current memory circuit designs. Because the typical row decoder structures in the prior art use the same gate circuitry (e.g., standard NAND or NOR gates) for both selection and de-selection, the gate capacitances of the paths are coupled. Accordingly, if attempts are made to reduce the gate capacitance of the de-selection path (so as to increase the forward path speed) by reducing the size of the de-selection transistors, the de-selection path slows down, thereby adding to the overall cycle time.
SUMMARY OF THE INVENTION
Accordingly, the present invention advantageously provides a reduced latency row (i.e., wordline) selection scheme, preferably for use with high speed memory compilers, whereby the select and de-select paths in the row decoder are de-coupled such that each path may be individually optimized. In one aspect, the present invention is directed to a wordline selection circuit for selecting a wordline in a memory array based on a plurality of row address signals. The circuit comprises a row pre-decoder circuit portion to generate a decoded wordline clock (DXC) signal from a row decode select clock (XC) signal in response to the plurality of row address signals. A row decoder circuit portion is included to generate a wordline select (XWL) signal in response to the DXC signal and the row address signals. A dummy wordline (DWL) signal generator produces a DWL signal in response to the DXC signal, wherein a dummy read/write memory cell (which mimics the memory cell current) is selected by driving a dummy wordline with a dummy row decoder. A dummy read bitline (DBL) signal generator produces a DBL signal in response to the DWL signal. A wordline shutdown clock (SDB) signal generator produces an SDB signal in response to the DBL signal. Responsive to the DBL signal, the row pre-decoder circuit portion de-activates the DXC signal, preferably at the same time as or prior to the activation of the SDB signal. In addition, responsive to the SDB signal, the row decoder circuit portion de-activates the XWL signal, thereby de-selecting the wordline.
In another aspect, the present invention is directed to a memory compiler for use with designing an integrated semiconductor device having an embedded high-speed memory instance. The memory compiler comprises a memory macro cell associated with the embedded memory instance, which includes an array or core disposed with dummy wordlines, dummy read/write memory cells, dummy read/write bitlines, and a dummy row decoder driving the dummy wordlines. Circuitry is provided for driving a wordline select signal HIGH to select a wordline in the memory array core responsive to a clock signal and a plurality of row address signals. Circuitry for driving the wordline select signal LOW (thereby de-selecting the wordline) is included, which operates based on a shutdown clock signal generated in response to a dummy read bitline signal. The gate logic of the circuitry for de-selecting the wordline is de-coupled from the gate logic of the circuitry for selecting the wordline.
REFERENCES:
patent: 4989182 (1991-01-01), Mochizuki
patent: 5475640 (1995-12-01), Kersh, III et al.
patent: 5694369 (1997-12-01), Abe
patent: 5793698 (1998-08-01), Koarek et al.
patent: 5926430 (1999-07-01), Noda et al.
patent: 5959906 (1999-09-01), Song et al.
patent: 5970001 (1999-10-01), Noda et al.
Ho Hoai V.
Smith ,Danamraj & Youst, P.C.
Virage Logic Corp.
LandOfFree
Reduced latency row selection circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reduced latency row selection circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduced latency row selection circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2881287