Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-04-12
2002-05-07
Mai, Son (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S194000
Reexamination Certificate
active
06385127
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a synchronous semiconductor device, and in particular, to a method of latching an input signal to a synchronous semiconductor device.
In a synchronous semiconductor device such as synchronous dynamic random access memory (SDRAM), there are demands for reducing the set-up time and the set-up/hold time for input signals (command signal and address signal) which follow a clock signal in order to accommodate for the acceleration of the synchronous clock cycle.
Japanese Unexamined Patent Publication No. Hei 8-17182 discloses a synchronous semiconductor device according to a first prior art. A decoder which precedes a latch circuit is provided in the semiconductor circuit to enable a rapid internal operation. As a consequence, the decoding rate of the decoder has a direct influence upon the set-up/hold time.
The first prior art semiconductor device includes a logic circuit disposed between an external command input terminal and the latch circuit. The logic circuit decodes an external command signal fed to each external command input terminal, and the decoded signal is held by the latch circuit in synchronism with the clock signal. This technique is commonly referred to as “command prefetch approach”.
FIG. 1
is a block diagram of a command decoder circuit
60
of a synchronous semiconductor device according to a second prior art. The command decoder circuit
60
operates according to the command prefetch approach. Specifically, the command decoder circuit
60
includes a decode circuit
51
connected between four external command input terminals T
1
-T
4
and a latch circuit
50
. The decode circuit
51
includes a decode unit
52
having six AND circuits
52
a
-
52
f
, and four input buffers
53
a
-
53
d
. Clock signal CLK is fed to an external clock signal input terminal T
0
and passed through a clock buffer
54
to the latch circuit
50
. External command signals applied to the input terminal T
1
-T
4
are passed through corresponding input buffers
53
a
-
53
d
, respectively, to the decode unit
52
, which then decodes the external command signals to provide decoded signals, which are in turn received and held by the latch circuit
50
in synchronism with the clock signal CLK.
FIG. 2
is a block diagram of one of the input buffers
53
a
-
53
d
. Thus any one of the input buffers
53
a
-
53
d
includes a level conversion circuit
56
, a delay circuit
57
connected to the level conversion circuit
56
, an inverter circuit
58
connected to the delay circuit
57
and an inverter circuit
59
connected to the inverter circuit
58
. In each of the input buffers
53
a
-
53
d
, the delay circuit
57
controls the signal input to the decode unit
52
, whereby the set-up/hold time for each external command input terminal T
1
-T
4
is controlled.
Japanese Unexamined Patent Publication No. Hei. 9-153279 discloses a semiconductor device according to a third prior art. This semiconductor device also includes a decoder which precedes a latch circuit. Specifically, the semiconductor device includes a plurality of external command input terminals, D-type flip-flop circuits each for temporarily storing one of a plurality of external command signals applied to the plurality of external command input terminals, and a plurality of command decode circuits. The D-type flip-flop circuits deliver the plurality of external command signals which they temporarily store to the respective command decode circuits. The plurality of command decode circuits operate to decode the external command signal delivered from the D-type flip flop circuit to provide decoded signals, which are then supplied to a plurality of latch circuits to be held therein. At this time, a clock signal which depends on the delay time of an associated command decode circuit is fed to each latch circuit, thus enabling it to latch the decoded signal in accordance with the corresponding clock signal.
The first prior art semiconductor device has an access time which is more rapid than the access time of a semiconductor device in which a latch circuit precedes a logic circuit. However, a decoder having multiple stages of circuits and elements is connected between the external command input terminal and the latch circuit, and this results in a relatively long time interval or delay time from a point in time when an external command signal is applied to an external command input signal until the logic circuit delivers a decoded signal by decoding the external command signal. As a consequence, the set-up/hold dead zone of the decoded signal relative to the clock signal will be offset toward the set-up side. In other words, the set-up time of the decoded signal will be shortened.
With the semiconductor device according to the first prior art, the delay time within the logic circuit varies from decoded signal to decoded signal as a result of the potential transition situation of the external command input terminals and operational noises of the semiconductor device.
Consequently, the total dead zone in the set-up/hold of the decoded signal relative to the clock signal further increases.
By contrast, in the command decoder circuit
60
shown in
FIG. 1
, the delay circuit
57
controls the set-up/hold time for each external command terminal. However, a delay time from the transition of the potential of the signal applied to each external command input terminal T
1
-T
4
to the transition of a potential occurring in the decoded signal from each of AND circuits
52
a
-
52
f
varies from decoded signal to decoded signal. In addition, the delay time of the decoded signal D
1
-D
6
changes depending on the direction of transition of the potential on each external command input terminal T
1
-T
4
(i.e, from H level to L level or from L level to H level).
In addition, the delay time of the decoded signal D
1
-D
6
changes due to operational noises of the semiconductor device such as a variation in the supply voltage, for example. By way of example, if the command decoder circuit
60
is used in a synchronous DRAM, the following difficulties are experienced:
A mode register set command or self-refresh command is applied to a semiconductor device during its idle condition where the operational noises of the semiconductor device remain relatively low. By contrast, an active command, a read/write command or a precharge command is applied to the semiconductor device during its active condition where the operational noises are relatively high. Accordingly, with the active command, the read/write command and the precharge command, a variation in the set-up/hold time attributable to noises in the AND circuits
52
a
-
52
f
of the decode unit
52
is greater than a corresponding variation experienced by the mode register set command or the self-refresh command. In other words, there is a large variation in the set-up/hold time between different processing commands.
It is difficult to adjust such variation by using a plurality of delay circuits
57
in each of the input buffers
53
a
-
53
d
which precedes the decode unit
52
. Specifically, to accommodate for such variation, it would be necessary to choose an individual delay time for each of the plurality of delay circuits
57
, but in practice, such control would be difficult, and there remains a certain variation, which causes the dead zone breadth of the set-up/hold to increase when viewed from the whole assembly of external command input terminals T
1
-T
4
. If the command decoder circuit
60
is used in an address decode circuit or a variety of test mode decision circuits, a similar problem occurs.
For a semiconductor device including the input buffers
53
a
-
53
d
as shown in
FIG. 2
, there is a difference between a positive logic output circuit and a negative logic output circuit in the number of stages of constituting circuit elements. Obviously, there results an offset in the output timing between the positive logic output circuit and the negative logic output circuit, and this leads to an offset between the operations of AND circuits
52
a
-
52
f
Armstrong Westerman & Hattori, LLP
Mai Son
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