Test and diagnostics for a self-timed parallel interface

Details Test and diagnostics for a self-timed parallel interface Test and diagnostics for a self-timed parallel interface

1996-06-06

1998-07-28

Chung, Phung M.

Excavating

371 3701, 371 3707, 371 205, 39518505, G06F 1110, H03M 1300

Patent

active

057870942

ABSTRACT:
A method and apparatus that can test self-timed parallel interfaces operating at system speed. An output stage is provided for queuing a test packet and providing the test packet to an input stage. The packet contains a data bit stream and error detection code such as cyclic redundancy check code. The input stage is coupled to the output stage and receives the test packet to determine the correctness of the data bit stream. On the input stage, the error detection code verifier recalculates the error detection code and compares the recalculated error detection code with the error detection code attached to the data bit stream to determine the correctness of the data bit steam. The output queue has a first input port for receiving data from drivers on the interface and a second input port for receiving a pseudo random data bit stream. A pseudo random data generator generates a pseudo random data bit stream. The data bit stream may be packetized according to a predetermined protocol. An off-chip signal of the output stage may be provided to the inputs of the input stage to produce an on-chip copy of off-chip data.

REFERENCES:
patent: 3825905 (1974-07-01), Allen, Jr.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4811345 (1989-03-01), Johnson
patent: 5136592 (1992-08-01), Weng
patent: 5331274 (1994-07-01), Jarwala et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5390191 (1995-02-01), Shiono et al.
patent: 5394403 (1995-02-01), Klein
patent: 5416409 (1995-05-01), Hunter
patent: 5428714 (1995-06-01), Yawata et al.
patent: 5436554 (1995-07-01), Decker, Jr.
L. L. Buckel, L. V. Nguyen, P. J. Satz, R. E. Sepulveda and W. Sullivan, "RS/6000 Parallel Port Architectural Verification Loader Program," IBM Technical Disclosure Bulletin, vol. 37, No. 06A, Jun. 1994, pp. 287-289.

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