Nonvolatile semiconductor memory equipped with data latch...

Details Nonvolatile semiconductor memory equipped with data latch... Nonvolatile semiconductor memory equipped with data latch...

2001-10-12

2002-07-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185130, C365S185110, C365S185090, C365S185030, C365S185170

Reexamination Certificate

active

06418052

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory and, more particularly, a multi-level NAND EEPROM in which data of 2 bits (4-level) or more multi-bits can be stored.
EEPROM, which is one type of non-volatile semiconductor memory, comprises a floating gate electrode (charge storage layer) and a control gate electrode, and the data value stored in the respective memory cell thereof is determined depending on the charge amount in the floating gate electrode.
Normally, in one memory cell, 1-bit (2-level) data “0”, “1” is stored, but there has recently been developed a multi-level NAND EEPROM which can store therein data of 2 bits (4-level) or more multi-bits can be stored in each memory cell thereof.
FIG. 1
shows the essential portion of a 4-level NAND type flash EEPROM.
Here, it is added that this EEPROM is disclosed in the specification of Japanese Patent Application No. 9-124493 (filed on May 14, 1997).
A memory cell array 1 comprises a plurality of memory cells disposed in the shape of a matrix. These memory cells are constituted in such a manner that the data therein can be electrically rewritten. Further, in the memory cell array
1
, there are disposed a plurality of word lines (control gate electrodes), a plurality of bit lines and a source line connected in common to the sources of a plurality of (or all) memory cells.
Further, disposed close to the memory cell array
1
are a bit line control circuit
2
which controls the potential of the bit lines, etc. and a word line control circuit
6
which controls the potential of the word lines, etc.
The bit line control circuit
2
is provided, for instance, for outputting the data in memory cells in the memory cell array
1
to the outside of the chip via the bit line at the time of read, for detecting the state of memory cells in the memory cell array
1
at the time of verify, and for applying a program control voltage to memory cells in the memory cell array
1
at the time of program.
The bit line control circuit
2
includes a plurality of data latch circuits which can hold data corresponding to one page of the memory cell array
1
; and, by performing a read operation a plurality of times, the data corresponding to one page can be held at the same time in a plurality of data latch circuits. At the time of read, a column decoder
3
selects the plurality of data latch circuits one by one successively, so that the data corresponding to one page held in the plurality of data latch circuits is outputted serially outward the chip from a data input/output terminal
5
via a data input/output buffer
4
.
Further, at the time of program, the column decoder
3
selects the plurality of data latch circuits successively one by one, so that data corresponding to one page is serially inputted from the outside of the chip to the inside thereof and held in the plurality of data latch circuits in the bit line control circuit
2
. The data corresponding to one page which is thus held in the plurality of data latch circuits is programmed at the same time into the plurality of memory cells in the memory cell array
1
.
In case of an n-bit type memory, such processing operations as mentioned above are performed in n blocks at the same time.
The word line control circuit
6
selects one of the word lines in the memory cell array
1
and applies predetermined potentials corresponding to the read, program and erase modes to the one word line thus selected (selected word line) and the other word lines (non-selected word lines).
The memory cell array
1
, the bit line control circuit
2
, the column decoder
3
, the data input/output buffer
4
and the word line control circuit
6
are controlled by a control signal and control voltage generation circuit
7
.
In the 4-level NAND flash EEPROM constituted as mentioned above, the data value stored in the respective memory cell is determined by the amount of electric charges in the floating gate electrode.
More specifically, the state in which the amount of charges in the floating gate electrode is zero is referred to as a neutral state, and the state in which the floating gate electrode stores therein charges which are positive with reference to the neutral state is referred to as an erase state. Further, the erase state is made to correspond to data “0”. For example, the erase operation can be executed by applying a high potential (about 20V) to the substrate and the earth potential (0V) to the control gate electrode.
The program state is referred to a state in which the floating gate electrode stores therein charges negative with reference to the neutral state thereof and made to correspond to data “1”, “2” and “3”. However, the amount of charges in the floating gate electrode in its data “2” state is set so as to be larger than the amount of charges in the floating gate electrode in its data “1” state, and the amount of charges in the floating gate electrode in its data “3” state is set so as to be larger than the amount of charges in the floating gate electrode in its data “2” state.
For example, the program operation can be executed by setting the substrate, the source and the drain to the earth potential (0V), respectively, and applying a high potential (about 20V) to the control gate electrode.
The structure of the memory cells in the multi-level NAND EEPROM is substantially identical with the structure of the memory cells in a general NAND EEPROM, so that, in case of the multi-level NAND EEPROM in which the data amount storable in one memory cell is larger, the memory capacity of data can naturally be increased as compared with the general NAND EEPROM in which one bit data is stored in one memory cell.
However, generally in case data of 2 or more bits is stored in one memory cell, the reliability of the data lowers in proportion as the rewrite number is increased, with reference to the case where data of one bit is stored in one memory cell.
Therefore, it is very convenient to the user side if 1-bit (2-level) data can be stored in the memory cells in the memory cell array or data of 2 bits (4-level) or more bits can be stored in the memory cells in the memory cell array in accordance with the purpose in use.
Further, in case of the NAND type flash EEPROM, the memory cell array is constituted of a main area, a spare area for storing redundant bits, and a redundancy area for relieving the defective bits in the main area or the spare area.
Here is the demand that, as for the main area and the redundancy area, data of 2 bits (4-level) ore more bits should desirably be stored in one memory cell in order to increase the memory capacity, and, as for the spare area, data of one bit (2-levels) should desirably be stored in one memory cell in order to prevent the reliability of the data from being lowered even if the rewrite number is increased.
BRIEF SUMMARY OF THE INVENTION
It is the object of the present invention to provide a non-volatile semiconductor memory having a switching function to ensure that, as the data stored in one memory cell array, data of 2 bits (4-levels) or more multi-bits (more multi-levels) can be used or data of 1 bit (2-levels) can be used.
The non-volatile semiconductor memory according to the present invention comprises a memory cell array including memory cells arranged in a matrix form a memory cell selecting means for selecting the memory cells read or programmed simultaneously, a plurality of data latch circuits provided corresponding to memory cells selected by the memory cell selecting means, a means constituted in such a manner that the plurality of data latch circuits are grouped by m (m being 2 or a greater natural number) into sets, so that, when data comprising a plurality of bits is read from or programmed into each of the plurality of select memory cells, the means selects one data latch circuit, and, when one-bit data is read from or programmed into each of the plurality of select memory cells, the means selects m data latch circuits in one set, data input/output terminals for the transmission and reception o

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