Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
1999-12-17
2002-09-17
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S116000, C702S118000
Reexamination Certificate
active
06453258
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to dynamic logic macros having internal fixed-width pulse timing control and in particular to a system and method for optimizing burn-in testing of circuitry containing such macros. More particularly, the present invention relates to an improved burn-in test method and system whereby individual devices within dynamic logic macros are stressed for an adequate period during each burn-in cycle.
DESCRIPTION OF THE RELATED ART
Burn-in Testing
Burn-in testing generally refers to testing equipment by operating it under specified conditions for a specified period of time. Since, most hardware problems that occur in modern digital electronic systems occur in the first few hours of operation (so-called “infant mortality”), it is desirable to perform burn-in testing of such systems before they are sold.
Properly planned and conducted burn-in testing is a well-known method of reliability screening at the component level. By subjecting individual devices to the stress of burn-in test conditions which include temperature stress, electrical stress, temperature cycling, etc., a macro developer can identify specific faults that would be more difficult to perceive at the macro, module, or system level.
Self-Resetting Logic
Self-resetting dynamic logic macros have been designed in part to eliminate the need to utilize a system clock signal with which to correctly synchronize all logic operations within very large scale integrated (VLSI) circuitry. Such self-resetting circuitry has generally been implemented utilizing Complementary Metal Oxide Semiconductor (CMOS) technology and is thus commonly referred to as SRCMOS. Further background information relating to self-resetting dynamic logic circuitry may be found with reference to U.S. Pat. No. 5,434,519, U.S. Pat. No. 5,565,798, and U.S. Pat. No. 5,329,176 which are incorporated herein by reference.
The timing signals generated by self-resetting logic techniques are characterized as having a fixed pulse with respect to the input signals (often data input) which cause the triggering of self-reset circuits. Such fixed-timing signals are useful for internal clocking or strobing. When a self-reset initiated signal is utilized as a strobe (within a Programmable Logic Array (PLA) control module, for example) is it necessary to maintain the control path properly synchronized with related logic data transfer (the data path).
Due to ever increasing speed demands, microprocessor designs are often implemented utilized delayed-reset and self-resetting dynamic circuit macros. During normal operation, latches within such macros generate narrow, fixed-width pulses. The reset signal generated at the last stage of a dynamic logic pipe is a fixed-width pulse derived from the same clock edge that controls the input sampling latch. Thus, these macros operate internally with fast fixed-width pulses even with the typically slow clocking applied during burn-in testing. Many devices within such macros would thus be stressed for only a small fraction of the burn-in cycle time.
FIG. 1
is a high-level block diagram depicting the fixed control timing for a dynamic logic circuit
100
having a stretched output. As illustrated in
FIG. 1
, dynamic logic circuit
100
is a sequential logic structure which utilizes storage devices such as input latch
102
and output latch
108
to capture the output of each processing (logic) stage at the end of each clock period. During normal operation, latch
102
delivers fixed pulse width pulses from output
118
. Are set signal within logic block
104
is conventionally derived from a fixed-width pulse applied from a control input
112
derived from the same clock edge that controls latch
102
. Thus, dynamic logic circuit
100
operates with either an external or internally-generated reset signal typically having fast fixed-pulse widths even with the low global clock frequencies typical of burn-in testing.
A logic output from an output
120
of logic block
104
is stretched at pulse stretcher
106
in order to meet the receiving hold-time requirements of output latch
108
independent of internal timing control frequencies of reset signals from control input
112
. During normal operation of dynamic logic circuit
100
, a reset signal input
114
into pulse stretcher
106
is derived from global clock signal CLK
110
. Reset signal
112
, which resets logic within logic block
104
, may be derived from either CLK
110
or from control timing signals generated from the self-resetting technique described in firer detail with reference to
FIG. 2
or other clock-shaping techniques. Pulse widths of reset signals applied from reset inputs
112
and
114
are thus fixed and independent of the frequency of CLK
110
.
The generation of fixed-width control timing signals such as reset signals from reset input
112
, is depicted in
FIG. 2
, which is a schematic diagram illustrating fixed-timing characteristics of a conventional self-resetting circuit
200
. As shown in
FIG. 2
, self-resetting circuit
200
comprises a dynamic logic stage
202
and a reset delay path
203
. Dynamic logic stage
202
is a type of circuit known in the art as a domino circuit which includes a pre-charge device such as P-type field effect transistor (PFET,
208
, The gate terminal of PFET
208
is coupled to reset node
218
, the source terminal of PFET
208
is coupled to a supply voltage, V
dd
, and the drain terminal of PFET
208
is coupled to the input at dynamic node
204
of a logic network
214
.
Although not explicitly shown in
FIG. 2
, logic network
214
typically comprises a network of one or more interconnected N-type field effect transistors (NFETs) that may define a particular gate type, such as an AND or OR gate. Logic network
214
also receives one or more data input signals
216
that, depending upon the topology of its internal NFET network, define the conditions under which it discharges dynamic node
204
. The output of logic network
214
is connected to the source terminal of an evaluate device such as an NFET
210
. The gate terminal of NFET
210
is connected to the timing control signal provided at reset node
218
, and its drain terminal is connected to ground. It is through NFET
210
that logic network
214
discharges dynamic node
204
. A feedback of half-latch device, PFET
206
, is connected in parallel with PFET
208
, i.e., the node at which the drain terminal of PFET
206
is connected to V
dd
and its drain is also connected to dynamic node
204
.
Dynamic node
204
provides the input to an inverter
212
from which a data path continues at output node
205
which serves as the data output of self-resetting circuit
200
. The data path at output node
205
also serves as the origination of a “reset” signal that results when a signal at output node
205
is delayed a fixed amount as it propagates through self-reset module
203
. The resetting of dynamic circuit
202
and concurrent generation of fixed-width timing control signals is explained as follows. When input data
216
arrives, dynamic node
204
discharges to a logic low, causing output node
205
to go high. After propagating through inverters
207
,
209
, and
211
, the reset signal at node
218
goes low. Thus, after the delay through the self-reset loop, dynamic node
204
is pre-charged to a logic high. This process results in a fixed-width pulse generated at nodes
205
,
220
, and
222
all or some of which may be utilized as timing control signals for external circuits. The fixed-pulse width signal at node
205
propagates to the next logic stage.
This fixed-timing characteristic of dynamic logic self-resetting macros conflicts with one of the fundamental goals of burn-in testing which is to sufficiently stress individual devices. When burn-in testing has been conventionally applied to fixed-delay circuits, adequate testing of individual devices is often impossible even with extended testing. Therefore, although the burn-in operation is performed at very low frequencies, some devices are not stressed for
Aoki Naoaki
Dhong Sang Hoo
Silberman Joel Abraham
Takahashi Osamu
Bracewell & Patterson L.L.P.
Hoff Marc S.
Salys Casimer K.
Suarez Felix
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