Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-03-14
2002-08-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06436724
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to a method of monitoring the temperature of a rapid thermal anneal (RTA) process and a test wafer for use in this method, and more particularly to a method of monitoring the temperature of an RTA process by using a distorted surface structure of a semiconductor wafer in which surface reactions with a ambient reaction gas during an RTA process are induced.
2. Description of the Related Art
In state-of-the-art deep sub-micron CMOS manufacturing methods the accurate monitoring of the physical effects of a rapid thermal annealing (RTA) process on the semiconductor substrate is an indispensable procedure. For a given processing time, e.g. the electrical activation of previously implanted dopants in the semiconductor substrate (e.g., an Si-substrate) is strongly dependent on the temperature during the RTA process. More particularly, any inhomogeneities of the local temperature distribution across a semiconductor substrate during the RTA process will result in considerable local differences of the electrical activation and thus the local electrical conductivity values of doped regions in the semiconductor substrate. Such local variations are not acceptable in semiconductor manufacturing requiring high reproducibility and homogeneity in such RTA processes.
According to one of the conventional RTA temperature monitoring methods, the temperature dependency of the electrical conductivity of the previously ion-implanted semiconductor substrate is used as a measure of the temperature and the homogeneity of the local temperature distribution during the RTA process. In this method, the semiconductor substrate is a crystalline silicon test wafer that is, e.g., implanted by n-doping arsenic (As) ions at a dose of 10
16
ions/cm
2
and an implantation energy of 25 keV. The As ions are implanted evenly over the entire surface of the originally undoped and unstructured silicon test wafer. The silicon test wafer is placed in an RTA process chamber as a dummy and after performing the RTA process, the conductivity-dependent sheet resistance is measured at different locations on the silicon test wafer. Due to the strong temperature dependency of the electrical conductivity, variations in the sheet resistance which in turn depends on the electrical conductivity are a good indicator for temperature inhomogeneities. As an example, using the above ion implantation and performing an RTA annealing at 1,000° C. for 30 seconds typically results in a sheet resistance of about 74 &OHgr;/□(Ohm/Square).
Therefore, the standard monitoring of the RTA temperature is generally based on the resulting electrical activation of implanted dopants in silicon test wafers. However, low implantation doses of the As dopant ions in the silicon test wafers are accompanied by intrinsic variations in the sheet resistance independent of temperature inhomogeneities since implant doses below the solid-solubility limit will superimpose implant inhomogeneities. In this case, the variations of the sheet resistance across the silicon test wafer are a superimposition of variations of the solid-solubility and temperature inhomogeneities so that the reliability of this monitoring method is very limited.
On the other hand, by implanting high ion doses, the effect of this varying solubility on the sheet resistance is minimized. However, a longer implantation time is required for implanting high doses so that the operation time of the ion implanter is essentially increased resulting in high manufacturing costs for the silicon test wafers.
A further drawback of this first conventional monitoring method is that the silicon test wafers can only be used once. Thus, the use of these silicon test wafers as a monitoring means is lengthy and leads to high consumption of expensive test wafers.
In an alternative, second conventional approach for monitoring the RTA process, a mimic RTA process is performed in the RTA process chamber in an oxygen containing ambient. The oxygen is penetrating into the silicon test wafer during the RTA process and forming a silicon oxide surface film on the wafer. After this so-called RTO process (rapid thermal oxidation process), the resulting silicon oxide film thickness is measured as a monitoring means for the RTA process.
In
FIG. 1
, the solid lines RTO(T
1
) and RTO(T
2
) show the theoretical, exemplary time-dependency of the resulting oxide film thickness of this second method for two different RTA temperatures T
1
and T
2
, respectively, wherein the first temperature T
1
is lower than second temperature T
2
. The figure clearly shows that the silicon oxide film thickness is a very distinct function of both the annealing temperature and annealing time. However, this RTO technique is relatively insensitive due to the slow growth rate of the oxide film resulting in low film thickness. Due to the low film thickness, the measurement error of the film thickness measurement is high and the film thickness variations across the test wafer surface which result from temperature inhomogeneities during the RTA process may be hidden and undiscovered within the measurement errors.
Accordingly, there exists a need for a method of monitoring the temperature of an RTA process and a test wafer therefor enabling an accurate determination of the RTA process temperature and temperature distribution while keeping the monitoring costs low.
Further, there is a need to provide a method of reducing the number of consumed test wafers accompanied by a further reduction of monitoring costs.
The present invention is directed to a method that may solve, or reduce, at least some of the problems described above.
SUMMARY OF THE INVENTION
The present invention relates generally to a method of monitoring the temperature of an RTA process and a test wafer for use in this method, wherein a distorted surface structure of a semiconductor wafer is provided in which surface reactions with an ambient reaction gas during the RTA process are induced.
According to the present invention, the method of monitoring the temperature of a RTA process includes the steps of forming a distorted surface region in a semiconductor wafer, mounting the semiconductor wafer in a process chamber for performing the RTA process, performing the RTA process in a reaction gas ambient, and analyzing the reaction product film thickness of the semiconductor wafer. The reaction product film thickness is a sensitive measure for the temperature acting on the semiconductor wafer.
According to another aspect of the invention, a test wafer of a semiconductor material is provided for monitoring an RTA process in a reaction gas containing ambient. The crystalline structure of the semiconductor material is distorted at least in a defined area on one surface up to a predetermined depth. Due to the distorted surface, the penetration rate of the reaction gas atoms into the test wafer surface is essentially improved.
The present invention even further relates to a method of reworking a semiconductor wafer having a distorted surface region up to a predetermined depth after its use in a method of monitoring the temperature of an RTA process in a reaction gas ambient. During the RTA process, reaction gas compounds have penetrated into the distorted surface region and formed a reaction product film. After measurement of the reaction product film thickness, the reaction product film is removed by etching. Doing this, the reaction product-free semiconductor wafer surface is exposed and the wafer can be reused for another RTA monitoring process.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawing.
REFERENCES:
patent: 6017779 (2000-01-01), Miyasaka
Horstmann Manfred
Krüger Christian
Wieczorek Karsten
Advanced Micro Devices , Inc.
Niebling John F.
Stevenson Andre' C
Williams Morgan & Amerson P.C.
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