Circuitry for performing operations on binary numbers

Details Circuitry for performing operations on binary numbers Circuitry for performing operations on binary numbers

1999-06-18

2002-09-03

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S709000

Reexamination Certificate

active

06446107

ABSTRACT:

TECHNICAL FIELD
The present invention relates to circuitry for adding a binary number A to a binary number B and/or for summing binary number A, the binary number B and the number
1
, and, more particularly, the invention relates to circuitry that simultaneously provides the sum of the binary numbers A and B and the sum of the binary numbers A, B and 1. Other embodiments of the invention include circuitry for selectively summing the binary numbers A and B or the binary numbers A, B, and 1.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates known circuitry for summing the binary number A and the binary number B. The binary number A is represented as a series of bits a
i
where i is the binary weight of the bit a
i
and increases from the value zero for the least significant bit of A in steps of one to the value of the most significant bit of A. In the examples, A and B are eight bit numbers although only three bits are shown in FIG.
1
. The binary number B is a series of bits b
i
where i is the binary weight of the bit. The summation of the numbers A and B is represented by the binary number S which is a series of bits s
i
where i is the binary weight of the bit. The summation of the numbers A, B, and 1 is the number S′ which is a series of bits s′
i
, where i is the binary weight of the bit. The addition circuitry illustrated in
FIG. 1
receives as inputs the number A, the number B, and an initial carry-in value c
0
. The circuitry produces the number S if the initial carry-in value c
0
is zero and the number S′ if the initial carry-in value c
0
is one. The addition circuitry has a sequence of full adders. The first full adder receives the least significant bit of the numbers A and B and the initial carry-in value c
0
. It produces the least significant bit of the summation signal S or S′ and a first carry-in value c
1
. The second full adder has the binary weight of one, and receives the first carry signal c
1
and the bit values a
1
and b
1
. The second full adder produces as an output S
1
or S′
1
and the second carry value c
2
. There will generally be as many full adders serially interconnected as there are bits in the numbers A and B.
The relationship of the bits s
i
output from the full adders when the initial carry-in c
0
is zero to the bits a
i
and b
i
received is illustrated in equation 1. In this equation i represents the binary weight, a
i
is the ith bit of A, b
i
is the ith bit of B, g
i
is the bit generate, p
i
is the bit propagate, c
i
is the carry produced by the ith full adder and s
i
is the ith bit of S, the sum of A and B.
Equation 2 illustrates the relationship of the output of the ith full adder to the bit values a
i
and b
i
when the initial carry value c
0
is one. The symbol i represents the binary weight of a bit. a
i
is the ith bit of A, b
i
is the ith bit of B, g
i
is the bit generate, p
i
is the bit propagate, c
i
is the carry produced by the ith full adder and S′
i
is the ith bit of the number S′ which is the sum of A, B and 1.
Addition circuitry is commonly used to round a fractional number up or down to the nearest full number. By controlling the value of the initial carry-in value c
0
the output from the circuitry can represent either the rounded up sum S′, i.e. A+B+1 or the rounded down sum A, i.e., A+B.
Addition circuitry is also commonly used to find the difference between two binary numbers A and B where A and B are expressed as two's complement. When a number is expressed in two's complement format, it can be negated by either inverting all the bits of the number and then adding one or by subtracting one and then inverting all the bits of that number. Consequently, by performing appropriate inversions, addition circuitry can be used to create an output signal which represents a difference of two numbers.
In current video encoding standards, it is often necessary to find the absolute difference (i.e., unsigned (+ve) difference) between two numbers. According to the MPEG video encoding standards, the video is encoded by comparing how a picture changes frame by frame rather than reproducing the whole picture frame by frame. It is consequently necessary to determine whether a picture has changed from one frame to the next. This may be achieved by comparing a block of pixels in a frame to a number of blocks in the next frame to establish the block with the smallest difference. A number can be used to represent the attributes of a pixel. As attributes of the pixel change so does the number. Consequently, by comparing such numbers for one frame with the equivalent numbers for the next frame it can be deduced how the picture has changed from one frame to the next. It is therefore important in video encoding to be able to find the difference between two numbers. Normally, two separate circuits will be provided, one circuit that calculates the value of the first number minus the second number and another circuit that calculates the value of the second number minus the first number.
FIG. 2
illustrates in more detail addition circuitry
30
for summing A and B to produce S. The bit a
0
and the bit b
0
are supplied as inputs to an AND gate
2
0
which produces the bit generate g
0
. The bit a
0
and the bit b
0
are also supplied as inputs to an XOR gate
4
0
which produces s
0
as its output. The bit a
1
and the bit b
1
are supplied as inputs to an XOR gate
4
1
which produces the first bit propagate signal p
1
. The bit generate signal g
0
and the first bit propagate signal p
1
are supplied as inputs to an XOR gate
24
1
which produces the bit s
1
. The bit a
1
and the bit b
1
are also supplied as inputs to an OR gate
6
1
which supplies its output as a first input to an AND gate
8
1
. The second input of the AND gate
8
1
is received from the output of the AND gate
2
0
. The output of the AND gate
8
1
provides a first input to an OR gate
10
1
. The second input to the OR gate
10
1
is received from an AND gate
2
1
which receives as inputs the bit a
1
and the bit b
1
. The bit a
2
and the bit b
2
are supplied as inputs to an XOR gate
4
2
which provides its output as a first input to a XOR gate
24
2
. The second input to the XOR gate
24
2
is provided by the output of the OR gate
10
1
. The output of the XOR gate
24
2
provides the bit S
2
. The bit a
2
and the bit b
2
are also combined in an OR gate
6
2
to produce a first input to an AND gate
8
2
which receives as a second input the output from the OR gate
10
1
. The output from the AND gate
8
2
supplied as a first input to a OR gate
10
2
. The second input to the OR gate
10
2
is supplied by a AND gate
2
2
which receives as an input the bits a
2
and b
2
.
The output of the OR gate
10
2
is supplied as a first input to a XOR gate
24
3
. The second input to the XOR gate
24
3
is supplied by the output of an XOR gate
4
3
which receives as inputs the bit a
3
and the bit b
3
. The output of the XOR gate
24
3
provides the bit s
3
. An AND gate
2
3
also receives the bits a
3
and b
3
and provides its output as a first input to a OR gate
16
3
. The second input to the OR gate
16
3
is provided by an AND gate
14
3
which receives as a first input the output from the AND gate
2
2
and as a second input the output from an OR gate
6
3
which receives as inputs the bit a
3
and bit b
3
. The output from the OR gate
6
3
is also provided as a first input to an AND gate
12
3
which receives as a second input the output from the OR gate
6
2
.
The output from the AND gate
12
3
is supplied as a first input to an AND gate
8
3
which receives as a second input the output from the OR gate
10
1
. The output from the AND gate
8
3
and the output from the OR gate
16
3
are combined in an OR gate
10
3
. A XOR gate
24
4
receives as a first input the output from the OR gate
10
3
and as a second input the output from an XOR gate
4
4
which receives as inputs the bit a
4
and the bit b
4
. The XOR gate
24
4
produces the bit S
4
. An OR gate
6
4
rece

Affiliated with

Also associated with

Rating

Circuitry for performing operations on binary numbers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuitry for performing operations on binary numbers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuitry for performing operations on binary numbers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2879280