Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1997-02-05
2002-08-13
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S069000, C257S072000, C257S351000
Reexamination Certificate
active
06433361
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit in which a thin film insulated gate semiconductor device (thin film transistor, TFT) is formed on an insulating substrate and a method for the same. The insulating substrate represents an object having an insulating surface and includes an insulating material such as a glass and an object in which an insulator layer is formed on a material such as a semiconductor or a metal. In particular, the present invention relates to an integrated circuit using a material containing mainly a metal material such as aluminum, tantalum and titanium as a material of a gate electrode arrangement. A semiconductor integrated circuit of the present invention is used in an active matrix circuit and a peripheral driver circuit of a liquid crystal display or the like, a driver circuit of an image sensor or the like, an SOI integrated circuit, or a conventional semiconductor integrated circuit such as a microprocessor, a microcontroller, a microcomputer, or the a semiconductor memory.
In a case wherein an active matrix type liquid crystal display device, an image sensor or the like is formed on a glass substrate, a structure constructed by integrating thin film transistors (TFTS) is well known. In this structure, generally, after the first layer electrode arrangement (wiring) having a gate electrode is formed, an interlayer insulator is formed and then the second layer electrode arrangement is formed. If necessary, the third and fourth layer electrode arrangements are formed. In particular, in order to reduce a resistance of an arrangement, a metal material such as aluminum, tantalum and titanium is used as a material of each layer arrangement.
In an integrated circuit using TFTs, the second layer electrode arrangement is disconnected (broken) in an cross section portion (an overlap portion) of an electrode arrangement (gate wiring) extended from a gate electrode and the second layer electrode arrangement. This is because it is difficult to form an interlayer insulator on a gate electrode/arrangement with a superior step coverage and further planerize it.
FIG. 4
shows a disconnection state in a conventional TFT integrated circuit. In
FIG. 4
, a TFT region
401
and a gate electrode arrangement
402
is formed on a substrate, and an interlayer insulator is formed to cover the TFT region
401
and the gate electrode arrangement
402
. If the gate electrode arrangement
402
has a sharp edge, it cannot be sufficiently covered with the interlayer insulator
403
. In this state, when a second layer electrode arrangements
404
and
405
are formed, the second layer electrode arrangement
405
is disconnected in an overlap portion
406
.
In order to prevent such disconnection, it is necessary to increase a thickness of a second layer electrode arrangement (wiring). For example, it is desired that the thickness of the second layer electrode arrangement is about twice as thick as a thickness of a gate electrode arrangement. However, by increasing a thickness of the second layer electrode arrangement, a difference between a concave and a convex further increases in an integrated circuit. Also, when a further layer electrode arrangement is formed on the second layer electrode arrangement, a thickness of the second layer electrode arrangement must be determined in consideration of the disconnection. It is impossible to form a circuit in which an integrated circuit having an uneven surface is not desired, such as a liquid crystal display device, by increasing a thickness of the second layer electrode arrangement.
In an integrated circuit, if the disconnection occurs, since a whole circuit is defective, it is important to decrease the frequency of the disconnection.
SUMMARY OF THE INVENTION
The object of the present invention is to solve the above problems, that is, to decrease the frequency of the disconnection, thereby to increase a yield of an integrated circuit.
In the present invention, an oxide film is formed on at least upper surface of a gate electrode arrangement by oxidizing a gate electrode using anodization. Further, after insulators (side walls) having a substantially rectangular shape are formed on side surfaces of the gate electrode arrangement by anisotropy etching, an interlayer insulator is deposited and then the second layer electrode arrangement is formed. It is necessary not to etch easily the oxide film formed by anodization in comparison with a material constructing a side wall which is formed later. When side walls are formed using a silicon oxide, an aluminum oxide, a tantalum oxide, a molybdenum oxide, a tungsten oxide or the like is preferred. These material have an extremely low etching rate in a case wherein a silicon oxide is etched by dry etching using an etching gas including fluorine such as NF
3
and SF
6
.
In a method of an embodiment according to the present invention, an island semiconductor layer is formed, and then a film is formed as a gate insulating film on the island semiconductor layer. Also, a gate electrode/arrangement are formed. It is required that the gate electrode/arrangement are formed using a material to be anodized and a film obtained by anodization is not etched easily in comparison with a side wall.
After that, the gate electrode/arrangement are immersed into an electrolytic solution having approximately neutral to apply a positive voltage to it, so that an anodic oxide film is formed on at least upper surface of the gate electrode/arrangement. This process may be performed by vapor phase anodization. This is the first stage.
An insulating film is formed to cover the gate electrode arrangement and the surrounding anodic oxide film. In this film formation, coverage is important. Also, it is suitable that a thickness of the insulating film is about ⅓ to 2 times as thick as a thickness (height) of a gate electrode/arrangement. It is preferred to use chemical vapor deposition (CVD) such as plasma CVD, low pressure CVD, atmosphere pressure CVD or the like. Such formed insulating film is etched by anisotropy etching in an approximately vertical direction to a substrate. In etching completion, although the insulating film in an even portion is etched, the gate insulating film formed under the insulating film may be etched. As a result, in a step portion (a difference in height) such as sides of the gate electrode/arrangement, since the insulating film is thick, insulators (side walls) having a substantially rectangular shape remain. This is the second stage.
After an interlayer insulator is formed, a contact hole is formed in at least one of source and drain regions of a TFT, and then a second layer electrode arrangement is formed. This is the third stage.
In the above stages, there is several cases for doping to form source and drain regions of a TFT. When only N-channel type TFT is formed on a substrate, an N-type impurity having a relatively high concentration may be introduced into a semiconductor layer using the gate electrode and the surrounding anodic oxide film as masks in a self-alignment in q process between the first and second stages. When an anodic oxide film is formed on side surfaces of the gate electrode, so-called offset gate type TFT in which the source and drain regions are spaced apart from the gate electrode by a thickness of the anodic oxide film is obtained. As described below, a normal TFT includes such TFT.
When an N-channel type TFT having a low concentration drain (lightly doped drain, LDD), an LDD type TFT is formed, after an impurity having a relatively low concentration is introduced into a semiconductor layer in a process between the first and second stages, an N-type impurity having a higher concentration is introduced in the semiconductor in a self-alignment using a gate electrode and side walls as masks. A width of an LDD region is approximately equal to that of the side walls. When only P-channel type TFT is formed, the above process may be performed.
Also, a complementary type circuit (CMOS circuit) having N-channel type and P-channel ty
Suzawa Hideomi
Takenouchi Akira
Zhang Hongyong
Crane Sara
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Semiconductor integrated circuit and method for forming the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit and method for forming the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit and method for forming the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2878617