Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1996-09-30
2002-07-02
Chapman, Mark (Department: 1753)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S694000, C438S698000, C438S760000, C216S089000
Reexamination Certificate
active
06413870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to a process of manufacturing an integrated circuit chip and the integrated circuit chip formed thereby. More specifically, the present invention relates to the removal of scratches formed during chemical mechanical polish (CMP) steps by heating to a temperature high enough to cause the borophosphosilicate glass (BPSG) to reflow, thereby providing a smooth, planar surface.
2. Background Art
In the fabrication of integrated circuit (IC) chips, it is necessary to form a perfectly planar surface over gate topography in order to allow the subsequent layers to be properly aligned. In order to reduce topography associated with underlying structures, a borophosphosilicate glass is typically used, because it is a good dielectric substance that is also capable of being reflowed in order to eliminate voids and reduce topography. This planar surface is then overlaid sequentially with numerous layers of material which function as conductors, semi-conductors and insulators. Each subsequent layer is deposited and patterned usually by photolithographic techniques such that the sequence of layers form a complex array of electronic circuitry. However, the multiple layers can be formed only with difficulty unless the substrate topography is planarized in an early stage of the manufacturing process. The substrate topography must be as closely as possible to a planar surface throughout subsequent layer depositions because of problems associated with topography such as limited depth of focus during lithography, metal residues during reactive ion etching (RIE) and poor metal step coverage.
It is often necessary to polish a semiconductor wafer in order to remove topography, surface defects such as crystal lattice damage, scratches, roughness, or embedded particles such as dirt or dust. This polishing process is typically referred to as a chemical mechanical polish “CMP” and is utilized to improve the quality of and reliability of semiconductor devices. The CMP process is usually performed during the formation of various devices and interconnecting wiring on the wafer.
In general, the CMP process involves holding a thin flat wafer against a rotating wetted polishing surface under a controlled downward pressure. A polishing slurry such as a solution of alumina or silica may be used as the abrasive medium. A rotating polishing head or wafer carrier is typically utilized to hold the wafer under controlled pressure against a rotating polishing platen. The polishing platen is typically covered with a relatively soft wetted pad material such as a blown polyurethane.
A particular problem encountered in the CMP process is that micro scratches may be formed during the polishing process. These micro scratches are particularly damaging in inter-connection levels formed using the damascene technique because the metal layer that is deposited on the surface will become trapped in the scratch, thus causing short failure of the IC chip. Previously, this problem has been remedied to the extent possible by performing a touch-up CMP using a softer pad to try to eliminate the scratches, as shown in U.S. Pat. No. 5,514,245 issued to Doan et al. on May 7, 1996, assigned to Micron Technology, Inc. and incorporated herein by reference. However, although the touch-up CMP may minimize the scratch effect, it is difficult to remove the scratches without also over-polishing the entire layer. Also, this touch-up CMP adds time consuming process steps that must be carefully monitored and controlled to prevent the over-polishing. Therefore, there exists a need in the art to provide an inexpensive, reliable way to remove scratches formed during CMP steps of IC chip formation.
SUMMARY OF THE INVENTION
The present invention provides a process of manufacturing an integrated circuit chip using a reflow step to the oxide in order to remove scratches. Once the oxide has been subjected to the CMP process, the scratches may be removed by reflow. If BPSG is used as the interlevel dielectric, it may be reflowed at temperatures as low as 750° Celsius (C). Accordingly, the BPSG is reflowed and the scratches are removed, thereby enhancing the final yield of IC chips from the wafer, because fewer failures will have occurred due to shorts from metallized scratches.
This is also accomplished without the expensive and time consuming touch-up polish, as the process has only two variables, namely, time and temperature. Numerous other features and advantages of the present invention will become readily apparent from the following detailed description of the preferred embodiment, the accompanying drawings, and the appended claims.
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Chapman Mark
Neff Daryl K.
Schmeiser Olsen & Watts
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