Coating apparatus – Gas or vapor deposition – With treating means
Reexamination Certificate
2001-07-09
2002-07-16
Ghyka, Alexander G. (Department: 2812)
Coating apparatus
Gas or vapor deposition
With treating means
C118S7230ER, C438S766000, C438S787000, C438S788000, C438S795000, C438S798000
Reexamination Certificate
active
06418875
ABSTRACT:
TECHNICAL FIELD
The field of the present invention pertains to semiconductor fabrication processes. More particularly, the present invention relates to the field of adhering a layer of cap oxide with an incompatible layer of nanoporous silica.
BACKGROUND ART
The power and usefulness of today's digital integrated circuit (IC) devices is largely attributed to the increasing levels of integration. More and more components (resistors, diodes, transistors, and the like) are continually being integrated into the underlying chip, or Integrated Circuit (IC). The starting material for typical ICs is high purity silicon. The material is grown as a single crystal and takes the shape of a solid cylinder. This crystal is then sawed (like a slice of bread) to produce wafers typically 10 to 30 cm in diameter and 250 microns thick.
The geometry of the features of the IC components are commonly defined photographically through a process known as photolithography. Very fine surface geometry can be accurately reproduced by this technique. The photolithography process is used to define component regions and build up components one layer on top of another. Complex ICs can often have many different built up layers, each layer having components, each layer having differing interconnections, and each layer stacked on top of the previous layer. The resulting topography of these complex IC's often resemble familiar terrestrial “mountain ranges,” with many “hills” and “valleys” as the IC components are built up on the underlying surface of the silicon wafer.
Submicron devices, e.g. transistors smaller than 1 micron in size, are formed in the various layers that form the IC. Thousands or millions of the submicron devices can be utilized in a typical IC. However, circuits are continually becoming more complex and more capable. Hence, there is a constant need for increasing the number of components that are included on an IC. However, the size of an IC is frequently limited to a given die size on a wafer. Consequently, a constant need arises to reduce the size of devices in an IC.
As device size shrinks, the electrical Resistance-Capacitance (RC) delays and crosstalk associated with backend metallization become more significant. At some point, a threshold between the size of the device and the amount of interference it can sustain, is crossed. After this threshold, the operation of the device is compromised. Hence, a need arises to reduce the RC sensitivity of a deep submicron device.
One conventional method that reduces RC sensitivity of a device and an IC, uses low dielectric constant materials, k, for deep submicron devices. However, low dielectric materials have material properties that are incompatible with subsequent materials deposited thereon. Additionally, the low dielectric materials have material properties that are detrimental in the Chemical Mechanical Polishing (CMP) process. Resultantly, a need arises for modifying the low dielectric material to make it more compatible with subsequent material layers and with CMP processes.
Referring now to prior art
FIG. 1
, a wafer with a conventional porous material layer interfaced with a conventional cap layer is shown as a side view of. Wafer
100
includes a substrate
102
, a porous material
104
, and a cap layer
106
. Porous material
104
is deposited on top of substrate
102
. And cap material is deposited on top of porous material
104
. Porous material
104
is used because it has a low dielectric constant. However, a low dielectric material typically has low mechanical strength. Additionally, the porous material becomes impregnated with the CMP slurry during polishing. The slurry impregnated in porous material
104
causes other problems such as out gassing in subsequent high temperature processes and a high dielectric constant which hampers its operational ability. Thus, a cap layer, e.g. cap layer
106
, is required on top of porous material
104
to make it at least marginally compatible with subsequent semiconductor fabrication operations, such as CMP. Consequently, cap layer
106
is deposited on top of porous material
104
. Thus, cap layer
106
is used as a sacrificial layer for CMP planarization of the metal topography.
Besides these drawbacks, conventional porous layer
104
, of prior art
FIG. 1
, has a top surface that is significantly rough, as indicated by peaks
108
b
. Because of the porosity and the rough and irregular top surface of porous layer
104
, cap layer
106
has very poor adhesion to porous layer
104
. Consequently, a need arises for a method and an apparatus that provides a smoother and less porous surface for the porous layer so as to improve the adhesion between the porous layer and the cap layer.
Because of the poor adhesion, cap layer
106
frequently delaminates during the CMP operation. Delamination of cap layer
106
from porous layer
104
occurs in damascene processing as well as during copper and aluminum CMP processing. Consequently, a need arises for a resilient interface between the porous layer and the cap layer such that CMP operations can be performed without delamination.
In summary, a constant need arises to reduce the size of devices in an IC and to reduce the RC sensitivity of a deep submicron device. Additionally, a need arises for modifying the low dielectric material to make it more compatible with subsequent material layers and with CMP processes. Furthermore, a need arises for a method and an apparatus that provides a smoother and less porous surface for the porous layer so as to improve the adhesion between the porous layer and the cap layer. Yet another need arises for a resilient interface between the porous layer and the cap layer such that CMP operations can be performed without delamination.
DISCLOSURE OF THE INVENTION
The present invention provides a method to reduce the size of devices in an IC and to reduce the RC sensitivity of a deep submicron device. Additionally the present invention provides a method for modifying a low dielectric material to make it more compatible with subsequent material layers and with CMP processes. The present invention also provides a method for making, and an apparatus having, a smoother and less porous surface for the porous layer so as to improve the adhesion between the porous layer and the cap layer. And the present invention provides a resilient interface between the porous layer and the cap layer such that CMP operations can be performed without delamination.
Specifically, one embodiment of the present invention provides a method of improving adhesion of a cap oxide to a nanoporous silica, for integrated circuit fabrication. In the present embodiment, the method comprises several steps. The first step is to receive a wafer in a deposition chamber. Then a porous layer of material is deposited on the wafer. Next, a portion of the porous layer is densified in order to make it more compatible for adhesion to a cap layer. The step of densification is performed by exposing the top surface of the porous layer to a high density plasma. The high density plasma is a stream of high density Argon (Ar) ions, directed toward the wafer. Beneficially, ion bombardment using high density Ar ions has a self-limiting property that prevents densification from occurring beyond a certain depth in the porous layer. Finally, a cap layer is deposited onto the porous layer.
Another embodiment of the present invention implements the method of improving adhesion between a porous layer and a cap layer on a wafer by using a processor and memory. The steps provided in the previous paragraph are implemented as data and instructions of the memory to be executed by the processor.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
REFERENCES:
patent: 5866476 (1999-02-01), Choi et al.
patent: 6077386 (2000-06-01), Smith, Jr. et al.
patent: 6103601 (2000-08-01), Lee et al.
pa
Ghyka Alexander G.
Koninklijke Philips Electronics , N.V.
Zawilski Peter
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