Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-07
2002-05-21
Liang, Regina (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000
Reexamination Certificate
active
06392628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor display device. More specifically, it relates to a semiconductor display device which performs image display by driving pixel TFTs arranged in a matrix state, and to a semiconductor display device driving circuit. In addition, it relates to electronic equipment using such semiconductor display devices.
2. Description of the Related Art
Recently there has been rapid development in techniques of manufacturing semiconductor display devices, for example a thin film transistor (TFT), formed from semiconductor thin films on an inexpensive glass substrate. The reason for this is because the demand for active matrix type liquid crystal display devices has risen.
A TFT is placed in each of the several hundreds of thousands to several millions of pixel regions arranged in a matrix state on an active matrix type liquid crystal display device. The electric charge entering and exiting every pixel electrode is controlled by the switching function of the TFT arranged in the pixel regions.
The structure of a conventional active matrix type liquid crystal display device is shown in
FIG. 18. A
source signal line side driving circuit
1801
and a gate signal line side driving circuit
1802
are, normally, generically referred to as driving circuits. In recent years the driving circuit has been formed in unity with the pixel region, which is comprised of the pixel region, on the same substrate.
Further, source signal lines
1803
connected to the source signal line side driving circuit
1801
, and gate signal lines
1804
connected to the gate signal line side driving circuit
1802
, intersect in a pixel region
1808
. Pixel thin film transistors (pixel TFTs)
1805
, liquid crystal cells
1806
, which sandwich liquid crystals between a pixel electrode and an opposing electrode, and storage capacitors
1807
are formed in the regions surrounded by the source signal lines
1803
and the gate signal lines
1804
.
An image signal input to the source signal lines
1803
is selected by the pixel TFTs
1805
and written to a predetermined pixel electrode.
Sampling is performed on the image signal in accordance with a timing signal output from the source signal line side driving circuit
1801
, and the image signal is supplied to the source signal lines
1803
.
The pixel TFTs
1805
operate in accordance with a selection signal input from the gate signal line side driving circuit
1802
, via the gate signal lines
1804
.
[Prior Art A]
A block diagram of an example of the conventional source signal line side driving circuit
1801
is shown in FIG.
19
A.
An input signal input from external to the source signal line side driving circuit, a clock signal CLK (for example, 3 V), in this case, is input to the source signal line side driving circuit. The voltage amplitude level of the input clock signal is raised by a level shifter circuit (for example, from 3 to 16 V).
In the present specification the voltage amplitude level refers to the absolute value of the difference between the highest electric potential and the lowest electric potential of a signal. If the voltage amplitude level becomes higher (goes up), this means that the electric potential difference has become larger, and if the voltage amplitude level becomes lower, this means that the electric potential difference has become smaller.
Then the increased voltage amplitude level clock signal is input to the shift register circuit. The shift register circuit operates in accordance with the input clock signal, and a start pulse signal input at the same time to the shift register circuit, and creates a timing signal in order to sample the image signal. The timing signal is input to a sampling circuit, and the sampling circuit performs sampling of the image signal based on the input timing signal.
FIG. 21
shows an example of the specific circuit structure of
FIG. 19A. A
level shifter circuit
11
, a shift register circuit
12
, a sampling circuit
13
, and an image signal line
14
are arranged as shown in the diagram.
A clock signal CLK and an inverted clock signal CLKb are input to the level shifter circuit
11
, and a start pulse signal SP and a drive direction switching signal SL/R are input to the shift register circuit
12
from the wirings shown in the drawing.
The clock signal CLK (for example, 3 V) is input to the level shifter circuit
11
from external to the source signal line side driving circuit. It is necessary for the voltage amplitude level of the clock signal to be of a voltage amplitude level at which the level shifter circuit
11
can operate.
Further, unwanted radiation due to the clock signal is a problem of the set. Unwanted radiation is caused by generation of high frequency components of digital circuits which use rectangular wave trains starting up very sharply. Unwanted radiation becomes larger as the signal frequency gets higher, but it can be suppressed to a certain extent by reducing the voltage amplitude level of the signal.
It is necessary to suppress the unwanted radiation to within the range conforming to the standard established by CISPR (the International Special Committee on Radio Interference). Furthermore, in addition to CISPR, it is necessary that the range conform to the standards established by other foreign and domestic organizations such as the United States FCC (Federal Communications Commission), VCCI (Voluntary Control Council for Interference by data processing equipment and electronic office machines), and the German VDE (Verband Deutscher Elektrotechniker e.v). For example, the standard established by the FCCI states that, for industrial equipment, the permitted value of unwanted radiation is 1000 &mgr;V when the frequency is from 0.45 to 1.6 MHz, and is 3000 &mgr;V when the frequency is from 1.6 to 30 MHz. It is necessary to reduce the voltage amplitude level of the clock signal input from external to the source signal line side driving circuit to a level in which the unwanted radiation will conform to the standards established by the CISPR and other foreign and domestic standards and cause no trouble.
The voltage amplitude level of the clock signal input to the level shifter circuit increases. An equivalent circuit diagram of the level shifter circuit
11
is shown in FIG.
20
. The reference Vin denotes an input signal, and Vinb denotes an input of an inverted Vin. In addition, Vddh denotes the application of a positive voltage, and Vss denotes the application of a negative voltage. The level shifter circuit
11
is designed so that the signal input from Vin, made into a high voltage signal, and inverted, is then output from Voutb. In short, if Hi is input to Vin, then a signal corresponding to Vss is output from Voutb, and if Lo is input to Vin, then a signal corresponding to Vddh is output from Vout.
The voltage amplitude level of the clock signal is increased, by a level shifter like that shown in
FIG. 20
, to a voltage amplitude level that includes a certain fixed margin voltage in addition to a voltage amplitude level at which the liquid crystal is driven to a saturation state (liquid crystal saturation voltage). Further, saturation voltage indicates the liquid crystal saturation voltage in the present specification. A liquid crystal being driven into a saturation state indicates a state (saturation state) in which a change in the electro-optical characteristics following change in the liquid crystal arrangement will not accompany a further increase of the applied voltage.
The timing signal is a signal used in order to sample the image signal input to the sampling circuit. The voltage of the timing signal input to the sampling circuit is then applied to a gate electrode of a TFT which structures the analog switch of the sampling circuit. This forms a channel in the TFT which structures the analog switch, and a current flows from the source to the drain. Thus the image signal is sampled, and this is supplied to the source of the pixel TFT through the source signal line.
For exampl
Koyama Jun
Yamazaki Shunpei
Liang Regina
Peabody LLP Nixon
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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