Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-03-23
2002-05-14
Dang, Trung (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000, C438S296000, C438S424000, C438S435000
Reexamination Certificate
active
06388303
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, particularly to a trench isolation structure in a semiconductor device and a method of forming the structure.
2. Description of the Related Art
In recent years, with the high integration and high densification of ULSI, there has been an increasing demand for finer isolation films. A selective oxidation process, known as the Local Oxidation of Silicon process (LOCOS), has been used in a conventional isolation technique. In the selective oxidation process, the oxidation of a silicon substrate advances to the peripheral lower part of a silicon nitride film as an oxidation resistant mask, and a so-called bird's beak is formed. As a result, even when the width of the silicon nitride film formed as the mask on the surface of the silicon substrate is set to a minimum isolation width, an active region is reduced in size. Specifically, the reduction of the isolation width reaches its limit.
Moreover, when the bird's beak is formed in the periphery of the isolation part, the surface of the element isolation part becomes uneven and defects are caused in performing a photolithography process to form semiconductor devices on the active region of the semiconductor substrate, this makes it difficult to perform a fine processing.
A trench isolation process is proposed as a technique of solving the problem.
An example of the trench isolation process as described in Japanese Patent Application Laid-Open No. 8118/1997 will be described hereinafter with reference to
FIGS. 7A
to
7
C.
(1) After successively forming a silicon oxide film
52
, a silicon nitride film
53
, a polysilicon film
54
and a silicon oxide film
55
on the main surface of a semiconductor substrate
51
, a trench
56
is formed by the lithography process, which extends through the films and reaches the inner side of the semiconductor substrate
51
(see FIG.
7
A).
(2) After depositing a Boro-Phospho Silicate Glass (BPSG) film
57
as an isolating film on the entire main surface of the substrate
51
including the trench
56
, the BPSG film
57
is thermally treated to cause reflow whereby the surface of the BPSG film
57
is flattened (see FIG.
7
B).
(3) The BPSG film
57
, silicon oxide film
55
, polysilicon film
54
and silicon nitride film
53
are successively etched back, so that the
13
PSG film (isolating film)
57
is contained substantially completely in the trench
56
of the semiconductor substrate
51
(see FIG.
7
C).
In this conventional example, the silicon oxide film
52
remains in the active region divided by the trench
56
. However, the surface of the silicon oxide film
52
is roughened by the chemical solution (thermal phosphoric acid at about
160
° C.) used for removing the silicon nitride film and is also damaged by ion implantation so that its insulating film properties are deteriorated. As a result, the silicon oxide film
52
cannot be used as it is, for example, as the gate insulating film of an MOS transistor.
To overcome this, after the above-described conventional process, a thermal oxide film having excellent properties is usually formed by removing the silicon oxide film
52
using wet etching and subsequently thermally oxidizing the substrate surface (main surface).
However, in this case, as shown in
FIG. 8
, when the silicon oxide film
52
is removed, the BPSG film
57
embedded in the trench
56
is also influenced by the etching, and an edge
51
a
(hereinafter referred to as the trench edge) of the substrate
51
is exposed. Specifically, in the entire BPSG film
57
inside the trench
56
, the portion in the vicinity of the boundary with the substrate
51
(the inner wall surface of the trench
56
) is deposited in the initial stage of the forming process of the BPSG film
57
. This portion has a lower film quality than the other portions of the BPSG film
57
in the trench
56
, and has a higher etching rate than the other portions. Therefore, when the silicon oxide film
52
is removed, the upper end of the BPSG film
57
in the vicinity of the boundary is preferentially eroded, a recess
58
is formed on the inside of the trench
56
from the surface of the substrate
51
, and the trench edge
51
a
is exposed. As a result, the following problems occur.
(1) In the gate insulating film (silicon oxide film) formed after the silicon oxide film
52
is removed, because uniform oxidation does not occur in the trench edge
51
a
, the silicon oxide film in the vicinity of the trench edge
51
a
becomes thin, which causes the defective voltage resistance of the gate insulating film.
(2) When the gate electrode of a MOS transistor is configured to cover the active region and the upper part of the isolating film
57
, an electric field is concentrated in the trench edge
51
a
, thereby causing the off leak phenomenon or narrow channel effect in the transistor.
SUMMARY OF THE INVENTION
Wherefore, an object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device which solve the above-described problems.
To attain this and other objects, according to the present invention, there is provided a semiconductor device including a substrate in which a trench is formed on a main surface, and an isolating film formed in the trench. The isolating film has a main body region positioned in the trench, a first region protruding upward from the main body region and positioned above the main surface, and a second region formed as the region extended along the main surface from the side surface of the first region and having a smaller height of a vertical direction from the main surface than the height of the vertical direction of the first region.
According to the present invention, since a trench edge is covered with the second region of the isolating film formed in the trench, the trench edge is prevented from being exposed.
Moreover, in this case, a conductive layer may be formed to ride over the upper part of the isolating film from the main surface.
In this case, the height of the first region is greater than the height of the second region, and a step between the main surface and the top surface of the isolating film increases in a stepwise manner. Therefore, when the conductive layer is formed from the main surface over to the top surface of the isolating film, the thickness of the conductive layer in the boundary between the isolating film and the main surface becomes smaller than that in the conventional art. As a result, when this conductive layer is etched and processed as a wiring layer, such as a gate electrode extended from the main surface over to the top surface of the isolating film, an unnecessary conductive layer does not remain in the boundary, so that the wiring layer can be prevented from being energized in an unnecessary part in the boundary when the semiconductor device is in use.
Moreover, according to the present invention, there is provided a semiconductor device manufacture method including: (a) a step of forming a first insulating film on a main surface which is one surface of a substrate; (b) a step of forming a trench passed through at least the first insulating film and reaching the inside of the substrate; (c) a step of forming a second insulating film having an upper region protruded upward more than the top surface of the first insulating film in the trench; (d) a step of forming a third insulating film having properties different from those of the first insulating film in a boundary with the second insulating film on the first insulating film; and (e) a step of using the third insulating film as a mask to etch the first insulating film.
In this method, by using the third insulating film as the mask and etching the first insulating film, at least a part of the first insulating film under the third insulating film remains along the substrate surface (main surface) from the second insulating film, and therefore the trench edge is preve
Fujita Kazunori
Misawa Kaori
Armstrong Westerman & Hattori, LLP.
Dang Trung
Sanyo Electric Co,. Ltd.
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