Synchronous DRAM using column operation sychronous pulses...

Details Synchronous DRAM using column operation sychronous pulses... Synchronous DRAM using column operation sychronous pulses...

2000-09-21

2002-03-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06356507

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory, for example, a semiconductor memory to synchronize input of a command and write or read of data with an external clock, such as a synchronous DRAM.
In the case of semiconductor memory which synchronizes input of a command and write or read of data with an external clock, the operation of circuits in a chip is synchronized with some basic pulses, which are generated within the chip by using the external clock as a trigger. In such a semiconductor memory, an access time from input of read command to data output is determined by the number of pulses in the external synchronous clock. For example, in a synchronous DRAM, the number of the pulses in the external synchronous clock is called as CAS latency (CL) and it is important value for a specification. A column operation synchronous pulse, which is synchronized with the operation of the column system circuit within a chip, is generated at a timing to fill this value. Further, the timing of this column operation synchronous pulse is usually determined uniquely by the above CL. The same pulse can be used even if a column command represents “read” or “write”, since the pulse control is advantageously simplified when the column operation synchronous pulses of read and write are identical.
FIGS. 1
to
3
illustrate the above described conventional semiconductor memory, respectively.
FIG. 1
is a block diagram showing extractively a circuit in reference to the control of a column system basic pulse in the synchronous DRAM.
FIG. 2
is a circuit diagram showing a constitutional example of an input column address latch controller in the circuit shown in FIG.
1
.
FIG. 3
is a circuit diagram showing a column pulse transfer controller in the circuit shown in FIG.
1
.
As shown in
FIG. 1
, a circuit in reference to the control of the column system basic pulse in the synchronous DRAM comprises an external clock input buffer
11
, pulse generators
12
-
1
,
12
-
2
,
13
-
1
,
13
-
2
, delay circuits
14
-
1
,
14
-
2
, a CAS input buffer
15
, a RAS input buffer
16
, a CS input buffer
17
, a decoder
18
, a decoder and latch circuit
19
, a WE input buffer
20
, an input column address latch controller
21
, address input buffers
22
-
1
,
22
-
2
(ADD
1
, ADD
2
), address latches
23
-
1
,
23
-
2
, core buses
24
-
1
,
24
-
2
(addresses K
1
, K
2
), a burst length counter
25
, a column pulse transfer controller
26
, a column bank controller
27
, a DQ buffer
28
, a data line
29
, an off chip driver
30
, an output pulse generator
31
, transfer gates
32
-
1
to
32
-
7
,
32
-
9
to
32
-
12
, a column address decoder
33
, a memory cell allay
34
and an inverter
35
or the like.
As shown in
FIG. 2
, the above column address latch controller
21
is composed of a NAND gate
41
, a transfer gate
42
and inverters
43
,
44
,
45
.
Further, as shown in
FIG. 3
, the above column pulse transfer controller
26
is composed of a NOR gate
51
, transfer gates
52
to
54
and inverters
55
to
60
. A signal CL
2
OPN controls the transfer gate
52
to open the transfer gate
52
when the CAS latency is
2
. A signal CL
3
OPN controls the transfer gate
53
to open the transfer gate
52
when the CAS latency is
3
.
In
FIGS. 1
to
3
, in order to simplify the illustrations, it is shown that only one-sided MOS transistor gates of transfer gates
32
-
1
to
32
-
7
,
32
-
9
to
32
-
12
,
42
,
52
to
54
are provided with signals. However, other sided MOS transistor gates are provided with inverted ones of the above signals. Here, the transfer gates
32
-
1
to
32
-
7
,
32
-
9
to
32
-
12
,
42
,
52
to
54
are formed by connecting a current path of a P channel type MOS transistor and a current path of an N channel type MOS transistor in parallel.
In this example, two kinds of column system basic pulses are used for a column operation synchronization and a column address latch. These two kinds of column system basic pulses are activated at the same timing.
FIGS. 4 and 5
are timing charts for showing signal waveforms of the CL
2
and the CL
3
schematically.
FIG. 4
shows a signal waveform in the case that the CL
2
, i.e., the CAS latency is
2
and
FIG. 5
shows a signal waveform in the case that the CL
3
, i.e., the CAS latency is
3
, respectively.
As shown in
FIG. 1
, the external clock input buffer
11
is connected to two pulse generators
12
-
1
and
13
-
1
. As shown in the timing chart of
FIG. 4
, respective pulse generators
12
-
1
and
13
-
1
generate pulse signals Pa and Pb, which have different pulse widths each other, from leading edges of an external clock VCLK. These respective pulse generators
12
-
1
and
13
-
1
are connected to pulse generators
12
-
2
and
13
-
2
via delay circuits
14
-
1
and
14
-
2
, which are composed identically, respectively. These pulse generators
12
-
2
and
13
-
2
generate pulse signals Pa′ and Pb′ from edges of the above pulse signals Pa and Pb, respectively. The pulse generators
12
-
1
,
13
-
1
and
12
-
2
,
13
-
2
are identically composed. The pulse signals Pa′, Pb′ are obtained by shifting the pulse signals Pa, Pb for a certain period of time, respectively. In the present example, as described later, it is assumed that the pulse signals Pb, Pb′ are used for the column operation synchronous pules and the pulse signals Pa, Pa′ are mainly used for the column address latch pulse.
If the column access information is inputted from a command pin, a decoder
18
is connected to the CAS input buffer
15
, the RAS input buffer
16
and the CS input buffer
17
, respectively, to decode these signals and generate a column system activated signal Pc. Further, the decoder and the latch circuit
19
is connected to the WE input buffer
20
in addition to the CAS input buffer
15
, the RAS input buffer
16
and the CS input buffer
17
. If the inputted command is write, the decoder and the latch circuit
19
activates a write enable signal Pe. If the inputted command is read, it activates a read enable signal Pf, respectively.
When the column system activated signal Pc is activated, the input column address latch controller
21
outputs a column address entry pulse Pd. This pulse Pd opens the transfer gates
32
-
6
and
32
-
7
. Therefore, the address information of the address input buffers
22
-
1
and
22
-
2
are transferred to the address latches
23
-
1
and
23
-
2
in a column address counter
39
, so that addresses K
1
and K
2
of the core buses
24
-
1
and
24
-
2
are decided.
On the other hand, activation of the column system activated signal Pc allows the burst length counter
25
to be activated. The pulse signal Pb counts up the activated burst length counter
25
by number of times corresponding to the burst length. During this time, the activated burst length counter
25
is activating a burst operation activated signal Pg.
As understood from the circuit construction shown in
FIG. 3
, in the case that the CAS latency is
2
(CL
2
), the column pulse transfer controller
26
activates a column pulse transfer signal Pj soon after the burst operation activated signal Pg is activated. This column pulse transfer signal Pj opens the transfer gates
32
-
3
and
32
-
4
to transfer the pulse signal Pa′ to the column bank controller
27
as a column operation synchronous pulse Pp and transfer the pulse signal Pb′ to the address latches
23
-
1
and
23
-
2
in a column address counter
39
as a column address latch pulse Pq. At this time, by the inverter
35
, a inverted signal of the above column address latch pulse Pq is also transferred to the address latches
23
-
1
and
23
-
2
.
In the present example, there is a margin in the activating timing of the column pulse transfer signal Pj with respect to the timing for activating these pulse signals Pa′ and Pb′. Therefore, finding a logical OR of the column system activated signal Pc and the burst operation activated signal Pg, the column pulse transfer signal

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