Amplifiers – Hum or noise or distortion bucking introduced into signal...
Reexamination Certificate
1999-08-30
2002-04-23
Mottola, Steven J. (Department: 2817)
Amplifiers
Hum or noise or distortion bucking introduced into signal...
C330S277000
Reexamination Certificate
active
06377118
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a linearizer for a power amplifier, such as a power amplifier of a wireless microwave communication system.
If a power amplifier operates in a linear stage, the distortion is low and the efficiency is low. It is desirable that the operating point of a power amplifier is set as near the saturation point, where the amplifier output is saturated, as possible. In such a case, when the input power is increased and the amplifier output is saturated, the gain will be lowered and the power amplifier will not operate in the linear stage. The nonlinear operation will create a high distortion. The linearizer is provided to avoid such distortion and ensure power gain and reasonable efficiency of the power amplifier.
(2) Description of the Related Art
FIG.
13
A and
FIG. 13B
are diagrams for explaining gain characteristics of power amplifiers.
FIG. 13A
shows gain characteristics of single-frequency-input and multifrequency-input power amplifiers. A microwave input signal is supplied to the power amplifier of the type related to the present invention. The relationship between the input power and the power gain of each amplifier is shown in FIG.
13
A. The gain of the amplifier is generally held constant with an increase of the input power until a certain limit of the input power is exceeded. Hereinafter, a range of the input power in which the gain of the subject device can be held constant is called the linear region. If the input power exceeds the limit, the gain of the amplifier will be lowered with the increase of the input power.
FIG. 13B
shows a frequency distribution of input and output signals of a power amplifier. Suppose that a two-frequency input signal having frequencies “f
1
” and “f
2
” is supplied to the power amplifier. The power amplifier is subject to intermodulation due to the nonlinearity. The intermodulation causes the power amplifier to output harmonic signals, such as “
2
f
1
−f
2
”, “
3
f
1
−
2
f
2
”, “
2
f
2
−f
1
” and “
3
f
2
−f
1
”, in response to the input signal.
For example, a wireless transmitter requires a power amplifier which amplifies a multi-channel transmitting signal for a number of channels. If a single-frequency-input power amplifier which deals with only a single-frequency transmitting signal is used by the wireless transmitter, a corresponding number of such power amplifiers for the number of channels must be installed. This configuration provides the gain characteristics with an increased constant region with respect to the input power, but will make the wireless transmitter expensive. To reduce the cost, a multifrequency-input power amplifier which directly amplifies a multi-channel transmitting signal, derived from a number of single-frequency transmitting signals for a number of channels, is frequently used by the wireless transmitter.
As shown in
FIG. 13A
, the constant region with respect to the input power in the gain characteristics of the multifrequency amplifier is narrower than that in the gain characteristics of the single-frequency amplifier. Hence, with respect to the same magnitude of the input power, the multifrequency amplifier is more likely to create distortion due to the intermodulation or the like than the single-frequency amplifier.
A linearizer which is configured to eliminate such distortion of the power amplifier is known. For example, a predistortion-type linearizer, as shown in
FIG. 14
, is known.
The linearizer of
FIG. 14
generally has a distortion extracting module
101
and a distortion compensating module
102
. The distortion extracting module
101
includes a splitter
111
, a linear amplifier
112
and a distortion generating amplifier
113
. The distortion compensating module
102
includes a pair of phase shifters
121
and
122
, a pair of attenuators
123
and
124
and a mixer
125
. An input terminal is connected to an input of the splitter
111
, and an output of the mixer
125
is connected to an output terminal.
For example, when a two-frequency input signal having frequencies “f
1
” and “f
2
” is supplied to the linearizer of
FIG. 14
via the input terminal, the distortion extracting module
101
is subject to intermodulation due to the nonlinearity of the amplifiers
112
and
113
, similar to the above-mentioned power amplifier. The intermodulation causes each of the amplifiers
112
and
113
to output harmonic signals, such as “
2
f
1
−f
2
”, “
3
f
1
−
2
f
2
”, “
2
f
2
−f
1
” and “
3
f
2
−f
1
”, in response to the input signal.
As shown in
FIG. 15A
, the input signal (“f
1
”, “f
2
”), the harmonic signals (“
2
f
1
−f
2
”, “
3
f
1
−
2
f
2
”, “
2
f
2
−f
1
”, “
3
f
2
−f
1
”) and the inverted-phase harmonic signals are supplied from the distortion extracting module
101
to the distortion compensating module
102
.
As shown in
FIG. 15B
, the harmonic signals and the inverted-phase harmonic signals are canceled each other in the distortion compensating module
102
, and a two-frequency output signal having only the frequencies f
1
and f
2
is produced as a result of amplification of the input signal at the output of the distortion compensating module
102
. In this manner, the conventional linearizer of
FIG. 14
is effective in eliminating the distortion components from the output signal even when the multifrequency signal is input.
Further, as disclosed in Japanese Laid-Open Patent Application No. 57-101404, an FET-based linearizer is known. The conventional linearizer of the above publication includes a field-effect transistor (FET) having a drain connected to an input terminal, a gate connected to a bias line and a source connected to an output terminal. An input signal is supplied to the drain of the FET via the input terminal. A fixed bias voltage is supplied through the bias line to the gate of the FET. At the same time, the input signal is supplied through a variable resistor to the gate of the FET. An output signal is produced at the source of the FET as a result of amplification of the input signal, and the output signal is supplied from the source of the FET to the output terminal.
In the conventional linearizer of the above publication, the input signal is supplied through the variable resistor to the gate of the FET, in addition to the fixed bias voltage, and a bias point of the FET is shifted according to the magnitude of the input signal. Even when a large input signal is supplied to the FET, the conventional linearizer can prevent the lowering of the gain due to the increase of the input signal, and can compensate for the distortion of the output signal.
However, in the conventional linearizer of
FIG. 14
, the input signal is distributed to two signal processing routes. The extraction of the distortion components, and the phase matching and amplitude matching of the two signal processing routes must be carried out in order to allow the harmonic signals and the inverted-phase harmonic signals to be canceled each other. Hence, the linearizer of
FIG. 14
requires a large-size signal processing circuit, and the power consumption is large. Further, the phase and amplitude matching which allows for the distortion compensation is complicated.
Further, in the conventional linearizer of the above publication, the input signal is supplied through the variable resistor to the gate of the FET, in addition to the fixed bias voltage, and a bias point of the FET is shifted according to the magnitude of the input signal. The conventional linearizer of the above publication requires an optimization of the variable resistor for compensating for the distortion of the output signal. The adjusting of the resistor for the optimization is complicated. Further, it is necessary that the conventional linearizer of the above publication be connected to a low-pass filter as the subsequent-stage device of the linearizer.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved linearizer in which the above-mentioned pro
Sasaki Takao
Shigaki Masafumi
Fujitsu Limited
Mottola Steven J.
Rosenman & Colin LLP
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