Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-05-15
2002-07-02
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000
Reexamination Certificate
active
06414387
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices capable of sufficiently maintaining high frequency properties of high frequency semiconductor chips that operate at high frequencies, especially, in the gigahertz band.
BACKGROUND OF THE INVENTION
In recent years, demand has been growing for integrated circuits capable of operating at microwaves and milliwaves, in response to wide-spread use of mobile telecommunications systems such as PHSs (Personal Handy Phone System) and PDCs (Personal Digital Cellular Phone). Thus, Si and GaAs transistors have been developed for use in such integrated circuits, which in turn led to on-going development of highly integrated MMICs (Monolithic Microwave Integrated Circuits), such as power amplifiers, mixers, and low noise amplifiers, incorporating those transistors.
In an integrated circuit operating in a high frequency band, the stray inductance in wires grows beyond ignorable level. The stray inductance, in some cases, drastically degrades properties of the integrated circuit, especially, those properties in GHz range.
For example, to package or mount a semiconductor chip including a high frequency circuit on a circuit substrate, bonding wires are used so as to electrically connect the semiconductor chip to the package or circuit substrate. In that situation, the effect of the inductance of the bonding wires is extremely strong: the degradation in the intrinsic performance (especially, high frequency properties) of the circuit in the semiconductor chip is inevitable unless the inductance is reduced sufficiently.
Specifically, the effect of the inductance of the bonding wires as signal lines extending from the semiconductor chip can be reduced by matching impedances with an externally connected load circuit; however, such matching is impossible on the inductance of, especially, grounded bonding wires, which end up in behaving as a feedback circuit. Thus, the inductance reduces the gain introduced by the amplifier circuit in the semiconductor chip, and degrades properties, especially in high frequency band.
So, the problem here is how to minimize the inductance when the ground line in, for example, a gallium arsenide (GaAs) semiconductor chip for use at high frequencies is connected to an external ground line or ground surface, such as the package or the circuit substrate, so as to mount the semiconductor chip.
Conventionally, there are two kinds of techniques used popularly to reduce the inductance. One of them is to shorten the bonding wires to a minimal possible extent so as to reduce their inductance.
A typical example of techniques of this kind is described for use in mounting in “LDMOS Devices Provide High Power for Digital PCS”, Applied Microwave & Wireless, pp. 84-88, October (1988), by Cindy Blair.
In the course of mounting, a semiconductor chip is placed on a ground electrode, and bonding wires are positioned in parallel to each other and perpendicular to the sides of a high-frequency-use semiconductor chip, to minimize the length of, especially, the grounded bonding wires. Shown in
FIG. 5
is a schematic illustration of this mounting technique.
To further explain the mounting, as shown in
FIG. 5
, there is provided a package
80
including a ground electrode
81
for the package
80
, as well as input electrodes (lead frame serving as input terminals)
85
for the package
80
and output electrodes
86
for the package
80
disposed in proximity to the ground electrode
81
.
A semiconductor chip
71
disposed on the ground electrode
81
includes thereon a ground terminal
84
for ground use, input terminals
75
for the semiconductor chip
71
, and output terminals
76
for the semiconductor chip
71
.
The terminals
75
,
76
, and
84
of the semiconductor chip
71
are electrically connected respectively to the electrode
85
,
86
, and
81
of the package
80
by bonding wires
73
,
83
, and
82
.
Japanese Laid-Open Patent Application No. 2-107001/1990 (Tokukaihei 2-107001; published on Apr. 19, 1990), Japanese Laid-Open Patent Application No. 3-262302/1991 (Tokukaihei 3-262302; published on Nov. 22, 1991), etc. disclose another known technique to shorten the bonding wires whereby the bonding pads are positioned at the same height with the pattern surface of the substrate by arranging the chip so that the chip is connected to the bonding wires at places lower than the rest of the chip; hence, the bonding wires connecting the bonding pads to the pattern surface has a reduced length and a reduced inductance.
Another technique is known that shortens the wires in their entirety, including the bonding wires, whereby the high-frequency-use semiconductor chip is provided with a small hole through which the ground line inside the chip is connected to the external ground surface on the back of the semiconductor chip.
Apart from the foregoing kind of techniques to shorten the bonding wires, another kind of technique is known to reduce the mutual inductance, whereby the bonding wires extending from the ground line inside the semiconductor chip are provided in a maximum number possible and connect to the lead frame or to the slag right beneath the chip, so as to mount, and electrically connect, the high-frequency-use semiconductor chip to the package by wireless bonding. The technique is to connect a plurality of bonding wires having an inductance in parallel to each other so as to reduce the total inductance.
Incidentally, development in high integration of high-frequency-use semiconductor chips and increasing demand for smaller and cheaper circuits have resulted in a growing trend of a single high-frequency-use semiconductor chip incorporating circuits that have been conventionally offered as separately packaged high-frequency-use semiconductor chips. Shown in
FIG. 6
as an example is a schematic illustration of a high-frequency-use power amplifier (hereinafter, will be simply referred to as an amplifier circuit)
21
and an amplifier circuit
22
that are integrated into a single chip. As shown in
FIG. 6
, a high-frequency-use semiconductor chip
23
is constituted by an amplifier circuit
21
and an amplifier circuit
22
(
FIG. 6
only shows a bipolar transistor in the output stage).
The amplifier circuit
21
includes an output bonding pad
27
for the amplifier circuit
21
, a ground-use bonding pad
26
for the amplifier circuit
21
, and an input bonding pad
34
for the amplifier circuit
21
. The output bonding pad
27
is connected to, for example, the collector terminal of the high-frequency-use bipolar transistor, whereas the ground-use bonding pad
26
is connected to, for example, the emitter terminal of the high-frequency-use bipolar transistor.
Similarly, the amplifier circuit
22
includes an output bonding pad
24
for the amplifier circuit
22
, a ground-use bonding pad
25
for the amplifier circuit
22
, and an input bonding pad
36
for the amplifier circuit
22
. The output bonding pad
24
is connected to, for example, the collector terminal of the high-frequency-use bipolar transistor, whereas the ground-use bonding pad
25
is connected to, for example, the emitter terminal of the high-frequency-use bipolar transistor.
Further, a package
31
as the circuit substrate includes output terminals
32
and
33
for the package
31
to receive outputs from the amplifier circuits
21
and
22
respectively and input terminals
35
and
37
for the package
31
to supply inputs to the amplifier circuits
21
and
22
respectively, as well as a ground electrode
30
which serves as a frame to which the high-frequency-use semiconductor chip
23
is mounted and which also serves as a ground surface.
Then, bonding wires
50
,
41
,
38
,
39
,
28
,
29
electrically connect the bonding pads
34
,
36
,
27
,
24
,
26
, and
25
on the semiconductor chip
23
to the terminals (lead frame)
35
,
37
,
32
,
33
, and
30
of the package
31
respectively so as to electrically interconnect the semiconductor chip
23
to the package
31
. Among those bonding wires, the bonding wires
28
and
Asano Hiroyuki
Hara Shinji
Cao Phat X.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
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