Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-28
2002-09-10
Shankar, Vijay (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S068000
Reexamination Certificate
active
06448947
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel (hereinafter also referred to as “PDP”) and a plasma display device, and more particularly, it relates to a technique of reducing the scale of a common driver, reducing the cost and saving power.
2. Description of the Background Art
FIG. 22
is a block diagram typically showing the overall structure of a conventional plasma display device as first prior art. This structure is disclosed in Japanese Patent Laying-Open Gazette No. 7-160218 (1995) (Japanese Patent No. 2772753), for example. As shown in
FIG. 22
, a control circuit
106
generates prescribed control signals on the basis of an input clock signal CLK, image data DATA, a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC and outputs the control signals to an address driver
105
, a Y common driver
102
, a scan driver
103
and an X common driver
104
. The circuits
102
,
103
,
104
,
105
and
106
are supplied with prescribed voltages generated in a power supply circuit
107
.
The X common driver
104
and the address driver
105
generate prescribed voltages on the basis of the control signals from the control circuit
106
respectively, and output the voltages to sustain electrodes X
1
to XN and address electrodes A
1
to AM of three electrode plane discharge alternating plasma display panel (AC-PDP)
101
connected to output terminals of the respective drivers. The N sustain electrodes X
1
to XN are connected in common (therefore, these electrodes are also generically referred to as “sustain electrodes X”) and subjected to application of the same voltage. The Y common driver
102
generates a prescribed voltage on the basis of the control signal from the control circuit
106
and supplies the voltage to scan electrodes Y
1
to YN through the scan driver
103
for the PDP
101
.
FIG. 23
is a longitudinal sectional view of the PDP
101
disclosed in the aforementioned gazette. This figure illustrates the structure of a discharge cell C formed on the (three-dimensional) intersection between each pair of electrodes formed by each sustain electrode and each scan electrode and each address electrode shown in FIG.
22
.
As shown in
FIG. 23
, the PDP
101
has a front substrate
151
and a back substrate (or rear substrate)
161
arranged in parallel with each other through a discharge space
160
. A strip-shaped sustain electrode Xi (i: 1 to N) and a strip-shaped scan electrode Yi arranged in parallel with each other to define an electrode pair are formed on the surface of the front substrate
151
closer to the discharge space
160
along the direction perpendicular to the plane of
FIG. 23. A
dielectric or insulating layer
152
is formed to cover the aforementioned electrodes Xi and Yi and the aforementioned surface of the front substrate
151
. A protective film
155
consisting of a high secondary electron emission material such as magnesium oxide (MgO) is formed on the surface of the dielectric layer
152
closer to the discharge space
160
.
On the other hand, each strip-shaped address electrode Ak (k: 1 to M) is formed on the surface of the back substrate
161
closer to the discharge space
160
along the direction parallel to the plane of
FIG. 23
(see FIGS.
22
and
23
). A plurality of strip-shaped barrier ribs
163
are formed perpendicularly across the address electrode Ak, i.e., along the direction perpendicular to the plane of
FIG. 23
(the barrier ribs
163
may alternatively be formed in parallel with the address electrode Ak along cell boundaries).
A fluorescent substance layer
164
is formed on a region of the aforementioned surface of the back substrate
161
(and on the address electrode Ak) having no barrier ribs
163
(the fluorescent substance layer
164
may also be formed on side wall surfaces of the barrier ribs
163
). A dielectric or insulating layer may be formed on the surface of the fluorescent substance layer
164
closer to the back substrate
163
to cover the aforementioned surface of the back substrate
161
and the address electrode Ak.
A method of driving the AC-PDP disclosed in the aforementioned gazette is now described.
FIG. 24
is a timing chart showing the waveforms of the voltages applied to the respective electrodes in this driving method in a period of one subfield in a subfield gradation method.
As shown in
FIG. 24
, one subfield is divided into (a) a reset period for erasing wall charges remaining as the display history in a preceding subfield, (b) an address period for applying wall charges based on image data to discharge cells for generating display emission forming image display in a sustain period described later, and (c) a sustain discharge period or the sustain period for generating sustain discharge in the discharge cells storing the wall charges in the address period and performing display emission.
In the reset period, a full write pulse
24
is applied to the sustain electrode Xi at a time ta for generating discharge in all discharge cells. The full write pulse
24
is also referred to as a priming pulse. At a time tb when the full write pulse
24
falls, self-erase discharge is generated to erase wall charges of all discharge cells. In the subsequent address period, a scan pulse
21
is sequentially applied to the scan electrodes Y
1
to YN (at a time tc, for example) while an address pulse
22
based on the input image data DATA (see
FIG. 22
) is applied to the address electrodes A
1
to AM. Thus, address discharge is generated in discharge cells to be turned on for display in the sustain period for storing wall charges in the discharge cells. In the subsequent sustain period, a sustain pulse
23
is alternately applied to the scan electrode Yi and the sustain electrode Xi (see times td and te). At this time, only the discharge cells storing wall charges due to the aforementioned address discharge cause sustain discharge performing image display immediately after the rise of the sustain pulse
23
.
In the conventional driving method, the priming pulse
24
and the sustain pulse
23
are generated in the X common driver
104
and the Y common driver
102
and simultaneously applied to the full screen of the PDP. At this time, discharge simultaneously starts on the full screen or in all discharge cells, and hence the X common driver
104
and the Y common driver
102
supply an extremely large peak current to the PDP. The value of this peak current may reach 200 A in a PDP of 100 cm diagonal (type 40), for example. Therefore, circuits forming the common drivers
104
and
102
disadvantageously have remarkable power loss. Further, the X common driver
104
and the Y common driver
102
are required to have ability of supplying the current having the aforementioned large peak. Therefore, the X common driver
104
and the Y common driver
102
must be increased in circuit scale, to disadvantageously result in increase of the cost or the price of the common drivers
104
and
102
and the plasma display device.
Japanese Patent Laying-Open Gazette No. 7-64508 (1995) proposes an exemplary method capable of solving such problems.
FIG. 25
is a model diagram showing the structure of a plasma display device proposed in this gazette as second prior art. As shown in
FIG. 25
, the plasma display device according to the second prior art divides sustain electrodes X
1
to X
2
n
and scan electrodes Y
1
to Y
2
n
into two blocks, i.e., a block
201
a
including the sustain electrodes X
1
to Xn and the scan electrodes Y
1
to Yn and a block
201
b
including the sustain electrodes Xn+1 to X
2
n
and the scan electrodes Yn+1 to Y
2
n
, and is provided with dedicated sustain drivers (corresponding to the common drivers in the aforementioned conventional plasma display device)
202
a
,
202
b
,
204
A and
204
B for the respective blocks
201
a
and
201
b
. Referring to
FIG. 25
, a PDP
201
, an address driver
205
and scan drivers
203
a
and
203
b
correspond to the PDP
101
, the addre
Mitsubishi Denki & Kabushiki Kaisha
Patel Nitin
Shankar Vijay
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