Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-01
2002-05-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230060, C365S189090
Reexamination Certificate
active
06385091
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memories and in particular the present invention relates to a read reference scheme using current load matching on the reference word line path.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. One type of memory is a flash memory. A flash memory is a non-volatile memory. That is, a flash memory is a type of memory that retains data when its power source is removed. A typical flash memory comprises a memory array divided up into individually erasable sections or blocks of memory cells. The memory cells are arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. Moreover, each memory cell can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
To program a memory cell, a high positive voltage such as 12 volts is applied to the control gate of the cell. In addition, a moderate positive voltage such as 6 to 9 volts is applied to the drain while the source voltage and the substrate voltage are at ground level. These conditions result in the inducement of hot electron injection in the channel region near the drain region of the memory cell. These high-energy electrons travel through the thin gate oxide towards the positive voltage present on the control gate and collect on the floating gate. The electrons remain on the floating gate and function to increase the effective threshold voltage of the cell as compared to a cell that has not been programmed. A programmed non-volatile memory cell is said to be at a logic level of “0”. A block or section of memory cells is erased by putting a negative voltage on the word lines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements. In an erased state, the memory cells can be activated using a lower control gate voltage. An erased non-volatile memory cell is said to be at a logic level of “1”.
Verification of a non-volatile memory cell is accomplished by applying a potential to the control gate of the memory cell to be verified and then using a current sensing circuit or sense amplifier circuit to compare a current generated by the memory cell with a known current from a reference memory cell. The reference memory cell is generally a non-volatile memory cell or bit that has a predefined charge that is set or trimmed by the manufacture of the memory to produce a specific reference current. The reference cell is typically programmed to an intermediate state such that it conducts about half the current conducted by a fully programmed memory cell when an equivalent voltage level is applied to the control gates of the respective memory being read and reference memory cell. The reference memory cell is coupled to the sense amplifier circuit by a reference bit line line. Moreover, the memory cell that is being read is coupled to the sense amplifier circuit by a memory cell bit line.
To verify or read the state of a memory cell, a supply voltage is applied to a word line that is coupled to the control gate of the memory cell. At the same time, the same supply voltage is applied to a reference word line that is coupled to a control gate of the reference cell. The sense amplifier circuit then determines whether the memory cell to be read or verified draws more or less current than the reference current. By doing this, the sense amplifier circuit determines if the memory cell is in a programmed state or an erased state. However, a problem can occur in the prior art when differing current levels are drawn in a path between a voltage pump and word line verses a path between the voltage pump and the reference word line during a read or verify operation. A larger voltage drop from the supply voltage will occur in the path with the highest current load. This may cause a differential voltage to exist between the respective paths. Moreover, the differential may result in a reduction in the margin of current difference between the memory cell and the reference memory cell, which could reduce the accuracy of the sense amplifier circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved means of matching an active current in the voltage pump to word line path with the current in the voltage pump to reference word line path.
SUMMARY OF THE INVENTION
The above-mentioned problems with non-volatile memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a flash memory device is disclosed comprising, a word line, a reference word line and a reference load circuit. The word line is coupled to a control gate of a memory cell. The reference word line is coupled to a control gate of a reference memory cell. The reference load circuit is coupled to the reference word line to approximately match a current load on the word line so the voltage level of the reference word line will be approximately equally to the voltage level on the word line during a read operation.
In another embodiment, a flash memory device comprises, a voltage pump, a non-volatile memory cell having a control gate, a x-decoder circuit, a word line, a non-volatile reference memory cell having a control gate, a reference word line and a reference load. The voltage pump is used to supply a read voltage. The word line is coupled to the control gate of the memory cell. The x-decoder circuit is used to selectively couple the voltage pump to the word line during a read operation of the memory cell. The reference word line is coupled between the voltage pump and a control gate of the reference memory cell. In addition, the reference load circuit is coupled to the reference word line to provide a current load that approximately matches a current load of the x-decoder circuit.
In another embodiment, a non-volatile memory device comprises, a memory array, a voltage read pump, a x-decoder circuit, a non-volatile reference memory cell, a reference word line, a reference load circuit and a current sensing circuit. The memory array has a plurality of sectors of non-volatile memory cells arranged in columns and rows. The voltage read pump is used to supply a read voltage supply. The x-decoder circuit selectively couples an output of the voltage read pump to an addressed word line during a read operation. The word line is coupled to a control gate of a selected memory cell. The reference word line is coupled between the voltage read pump and a control gate of the reference memory cell. The reference load circuit is coupled to the reference word line to provide a current load that approximately matches a current load of the x-decoder circuit during the read operation. The current sensing circuit is used to compare currents in an array bit line coupled to the selected memory cell with a reference bit line coupled to the reference memory cell.
In another embodiment, a non-volatile memory system is disclosed. The non-volatile memory system includes an external processor, a memory array, control circuitry, a plurality of word lines, a voltage read pump, a x-decode circuit, a reference memory cell, a reference word line, a reference load circuit and a current sensing circuit. The external processor provides external read commands. The memory array has a plurality of array sectors. Each array sector has a plurality of memory cells. The control circuitry is used to control read operations to the memory array. Moreover, the control circuitry is coupled to receive the external read commands fro
Fogg Slifer Polglaze Leffert & Jay P.A.
Lam David
Lundberg Scott
Micro)n Technology, Inc.
Nelms David
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