Amplifiers – With semiconductor amplifying device – Including particular biasing arrangement
Reexamination Certificate
2001-08-30
2002-07-02
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including particular biasing arrangement
C330S288000
Reexamination Certificate
active
06414553
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is in the field of transistor amplifier circuits, and relates more particularly to a power amplifier circuit having a cascode current-mirror self-bias boosting circuit.
Amplifiers of this general type are frequently used in high-frequency RF amplifiers, as well as in audio amplifiers and other applications. In order to obtain a linear input-output relationship and high operating efficiency, such amplifiers are typically operated with a conduction angle of about 180° (Class B) or slightly greater (Class AB) to avoid crossover distortion.
Typically, amplifiers of this type require a dc bias circuit to establish the quiescent bias current in the amplifier circuit to ensure operation in the Class B or Class AB mode. In the prior art, bias is typically provided by a fixed current source, as shown in U.S. Pat. No. 5,844,443, or else by an external supply, which can be set to a desired constant value to secure the quiescent current necessary to operate in the desired mode, as shown in U.S. Pat. No. 5,548,248.
However, in amplifiers of the type described above the average current drawn from the supply depends upon the input signal level. As the output power increases so does the average current in both the emitter and the base of the power transistor. This increased average current causes an increased voltage drop in the biasing circuitry and in ballast resistors (which are used to avoid hot-spotting and thermal runaway in transistors using an interdigitated design). This in turn reduces the conduction angle (i.e. the number of degrees out of 360° that the amplifier is conducting), and forces the amplifier deep into Class B or even Class C operation, thereby reducing the maximum power output. To avoid this power reduction, the amplifier must have a larger quiescent bias. In prior-art circuitry this inevitably leads to a higher power dissipation at low power output levels and therefore an undesirable tradeoff in operating characteristics.
A recent improvement in this art is disclosed in co-pending and commonly-assigned U.S. patent application Ser. No. 09/536,946, entitled Dynamic Bias Boosting Circuit For A Power Amplifier, filed on Mar. 28, 2000. This application discloses a solution to the problem discussed above which entails providing the power amplifier circuit with a dynamic bias boosting circuit to dynamically increase the bias of the power transistor as the output power increases by using a circuit that senses the input voltage to the amplifier and generates a dynamic bias boost as a function of the amplitude of this signal. The drawback to this solution is that it employs numerous active and passive components, thus not maximizing simplicity, compactness and economy of manufacture.
Another recent improvement in this area is disclosed in co-pending and commonly-assigned U.S. patent application Ser. No. 09/730,657 entitled Self-Boosting Circuit For A Power Amplifier, filed on Dec. 6, 2000. This application presents an improved self-bias boosting circuit having an RC coupling network between the DC bias circuit and the amplifying transistor while using a generic DC bias circuit.
A scheme for independently controlling quiescent current and bias impedance is disclosed in High-Frequency Amplifier Circuit With Independent Control Of Quiescent Current And Bias Impedance, co-pending and commonly-assigned U.S. patent application Ser. No. 09/621,525, filed on Jul. 21, 2000. Although this scheme is capable of achieving high power-added efficiency while maintaining linearity, it employs a rather complex circuit and contributes a significant level of noise to the output stage.
All of the foregoing references are hereby incorporated by reference in their entirety.
Accordingly, it would be desirable to have a power amplifier circuit which offers the advantages of optimum maximum output power and reduced power dissipation at low power levels. Additionally, the circuit should be able to set the amount of self-bias boosting so that the power transistor can be properly biased for high power output and linearity as the power output increases, while controlling the quiescent current in the power transistor. Finally, it would be desirable for such a circuit to be extremely simple and compact in design, and very economical to manufacture.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a power amplifier circuit which provides improved maximum output power and less power dissipation at low power levels. It is a further object of the invention to provide a circuit which is able to set the amount of self-bias boosting so that the power transistor can be properly biased for high power output and linearity as the power output increases, while controlling the quiescent current in the power transistor. Yet a further object of the invention to provide a circuit which is both extremely simple and compact in design and which is very economical to manufacture.
In accordance with the invention, these objects are achieved by a new power amplifier circuit for amplifying an input signal and having a conduction angle of at least about 180°, the amplifier circuit including an amplifying transistor and a dc bias circuit for biasing the amplifier transistor to obtain the desired conduction angle. The dc bias circuit includes a self-bias boosting circuit which has a cascode current-mirror circuit having an output coupled to a control terminal of the amplifying transistor by a resistor, and a capacitor coupled from the cascode current-mirror circuit to a common terminal.
In a preferred embodiment of the invention, the cascode current-mirror circuit includes a first pair of transistors having main current paths connected in series, with the output of the current-mirror circuit being taken from a common point of this series connection, and a second pair of transistors having main current paths connected in series with a bias current source.
A power amplifier circuit in accordance with the present invention offers a significant improvement in that a particularly advantageous combination of features, including increased maximum output power, selectable self-bias boosting level, low-noise level, controllable quiescent current and reduced power dissipation at low power levels, can be obtained in an extremely simple, compact and economical configuration.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5548248 (1996-08-01), Wang
patent: 5724004 (1998-03-01), Reif et al.
patent: 5844443 (1998-12-01), Wong
patent: 6300837 (2001-10-01), Sowlati et al.
patent: 6333677 (2001-12-01), Dening
patent: 6344775 (2002-02-01), Morizuka et al.
US 000082, U.S. Ser. No. 09/536,946, Filed: Mar. 28, 2000.
US 000360, U.S. Ser. No. 09/730,657, Filed: Dec. 6, 2000.
US 000172, U.S. Ser. No. 09/621,525, Filed: Jul. 21, 2000.
Biren Steven R.
Choe Henry
Koninklijke Philips Electronics , N.V.
Pascal Robert
LandOfFree
Power amplifier having a cascode current-mirror self-bias... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power amplifier having a cascode current-mirror self-bias..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power amplifier having a cascode current-mirror self-bias... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2870645