Technique for making memory cells in a way which suppresses elec

Details Technique for making memory cells in a way which suppresses elec Technique for making memory cells in a way which suppresses elec

1993-03-11

1995-06-27

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 52, 437233, 437235, H01L 2170

Patent

active

054279674

ABSTRACT:
There is disclosed herein a technique for manufacturing a group of memory cells or devices on a common oxide coated silicon substrate such that the cells are arranged in rows and columns with row and column spaces separating the individual cells from one another. Each of the cells includes an array of different layers on the oxide coated top surface of the substrate including, in particular, the polysilicon layer. As disclosed, a method is provided for preventing the formation of polysilicon stringers between individual cells during their manufacture. This method is carried out by first forming the columns before the rows are formed such that continuous sidewalls of the columns are exposed to the ambient surroundings. Thereafter, these sidewalls are coated with protective layers, specifically layers of nitride.

REFERENCES:
patent: 4151021 (1979-04-01), McElroy
patent: 4462846 (1984-07-01), Varshney
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 5019879 (1991-05-01), Chiu
patent: 5081056 (1992-01-01), Mazzali et al.

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