Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-10-16
2002-05-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C327S277000
Reexamination Certificate
active
06388483
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit device and microcomputer that are intended for fast and low-voltage operation, and to a microcomputer system based on this microcomputer.
In order for a MOS transistor to operate at a low voltage around 1 V, it must have a lower threshold voltage for the enhancement of driving ability and operation speed. However, when the threshold voltage is set too low, the MOS transistor cannot turn off completely due to its subthreshold characteristics (tailing characteristics), causing a subthreshold leakage current to flow, resulting in an increased power consumption, as described in the “1993 Symposium on VLSI Circuits Digest of Technical Papers”, pp. 45-46 (May 1993).
As the sub-micron MOS transistor pattern design advances, the variation among devices of the fundamental characteristics including the threshold voltage attributable to the inequality of manufacturing process increases, as described in the “1994 Symposium on VLSI Circuits Digest of Technical Papers”, pp. 13-14 (June 1994).
FIG. 15
shows the variation of threshold voltage in connection with the gate length Lg of a MOS transistor. The variation of threshold voltage due to the gate length variation increases as the gate length Lg becomes shorter.
Assuming the lower limit of threshold voltage to be 0.2 V for making the subthreshold leakage current below a certain value and the above-mentioned process causing the threshold variation to be ±0.15 V, the actual lower limit of threshold voltage, which is the sum of these values, becomes 0.35 V.
On this account, conventional semiconductor integrated circuit devices cannot have their threshold voltage set much lower. Particularly, MOS transistors with lower power voltages operate in a state of incomplete saturation, and the operation speed of MOS transistor circuits falls sharply in response to a slight rise of the threshold voltage. Therefore, it is difficult for the conventional design methodology based on the worst-case consideration to attain the intended performance of semiconductor integrated circuit devices.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the foregoing prior art deficiency.
An object of the invention is to provide a semiconductor integrated circuit device formed of MOS transistors capable of properly arbitrating the conflicting factors of the increased power consumption caused by the subthreshold leakage current and the higher operation speed of MOS transistors.
Another object of the invention is to provide a semiconductor integrated circuit device capable of controlling the threshold voltage properly so that the power consumption and the operation speed are well balanced.
Still another object of the invention is to provide a semiconductor integrated circuit device capable of controlling the threshold voltage easily based on the external clock frequency.
Still another object of the invention is to provide a semiconductor integrated circuit device which is operative at multiple clock frequencies and capable of controlling the threshold voltage in correspondence to a selected clock frequency.
Still another object of the invention is to provide a semiconductor integrated circuit device capable of controlling the threshold voltage optimally for each MOS transistor even if it is unequal among individual transistors.
Still another object of the invention is to provide a microcomputer which is controlled to operate at an optimally balanced power consumption and operation speed, and a microcomputer system based on the microcomputer.
In order to achieve the above objectives, the inventive semiconductor integrated circuit device includes MOS transistors that constitute a main circuit and “delay-monitoring” MOS transistors that are provided in correspondence to the main-circuit MOS transistors these MOS transistors are operated under the corresponding substrate biases.
The operation speed or delay characteristics of the circuit is detected based on the comparison of a signal produced by the delay-monitoring MOS transistors with a clock signal or other reference timing signal. The substrate bias level is controlled based on the result of detection so that the main-circuit MOS transistors have an appropriate threshold voltage. The substrate bias level control is a sort of monitor control based on the delay-characteristic detecting transistors and the reference signal.
The difference of the delay characteristics of the circuit from the reference can be detected from a frequency error or phase error of the signal produced by the delay-monitoring MOS transistors with respect to the reference signal.
As a preferable arrangement, an oscillation circuit is designed such that the delay-monitoring MOS transistors determine the output frequency of the oscillation circuit. In this case, the delay characteristics are detected based on frequency error information that takes a continuous signal form derived from the oscillation signal.
According to a preferred embodiment of this invention, a main circuit that is a logic circuit is connected with a substrate-bias dependent oscillation circuit which shares the substrate bias with the main circuit and an operation-mode dependent oscillation circuit which switches the output frequency depending on the operation mode, and a substrate bias control circuit controls the substrate bias of the main circuit by making both oscillation outputs synchronous.
A semiconductor integrated circuit device according to a preferred embodiment of this invention includes a logic circuit which implements a certain logical operation, a control circuit which controls the threshold voltage of transistors that form the logic circuit, and a variable-frequency oscillation circuit, wherein the logic circuit includes MOS transistors formed on a semiconductor substrate, the oscillation circuit has its output delivered to the control circuit which also receives a reference clock of a certain frequency and adapted to produce a first control signal for controlling the oscillation circuit so that the oscillation output has a frequency correspondent to the frequency of the reference clock, and the MOS transistors of the logic circuit have their threshold voltage controlled by a second control signal that corresponds to the first control signal.
A semiconductor integrated circuit device according to a preferred embodiment of this invention comprises a logic circuit including MIS transistors formed on a semiconductor substrate, a control circuit which controls the threshold voltage of the MIS transistors of the logic circuit, and an oscillation circuit including MIS transistors formed on the semiconductor substrate and adapted to vary the output frequency, wherein the control circuit receives the output signal of the oscillation circuit and a clock signal of a certain frequency and compares the oscillation output frequency with the clock signal frequency to produce a first control signal, the oscillation circuit has its threshold voltage controlled by the first control signal so that the oscillation output has a frequency corresponding to the clock signal frequency, and the MIS transistors of the logic circuit have their threshold voltage controlled by a second control signal that corresponds to the first control signal.
A semiconductor integrated circuit device according to a preferred embodiment of this invention includes a logic circuit including p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable frequency including p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltages of these p-channel MIS transistors and n-channel MIS transistors, and a second oscillation circuit which produces reference clocks of different frequencies depending on the operation mode, wherein the control circuit receives one of the reference clocks and controls the first oscillation cir
Mizuno Hiroyuki
Nagano Takahiro
Nakagome Yoshinobu
Cunningham Terry D.
Mattingly Stanger & Malur, P.C.
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