Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-09-22
2002-07-09
Thompson, Craig (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
Reexamination Certificate
active
06417562
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to silicon verification generally and, more particularly, to embedding testbenches in silicon for verification.
BACKGROUND OF THE INVENTION
Testbenches are typically used in simulation to verify functionality. Evaluation boards are typically used in silicon verification to verify functionality on a volume scale. Simulation testbenches are usually constrained by slow simulation time.
Conventional testbench based verification is constrained to simulations only. No graceful link between simulation testbenches and silicon verification is normally provided with conventional systems. Typically, testbenches are hardcoded at the module level with little link to chip level.
Conventional testbenches have the disadvantages of not providing “at speed” verification. Additionally, simulation testbenches are slow. Debugging is more difficult with simulation testbenches. At times, significant effort is needed to re-create the debug issue in simulation software.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns a system for silicon chip evaluation comprising a chip embedded in a wafer and one or more testbench circuits embedded in the wafer, wherein the one or more testbenches provide verification of the chip. Another aspect of the present invention concerns a method for silicon chip verification comprising the steps of (A) embedding a chip in a silicon wafer, (B) embedding one or more testbench circuits in the silicon wafer, and (C) communicating between the one or more testbenches and the chip to provide silicon verification of the chip.
The objects, features and advantages of the present invention include providing a silicon testbench that may (i) be implemented using design software, (ii) provide “at speed” verification of a design by implementing the testbench at the silicon level, and/or (iii) provide verification at the silicon level.
REFERENCES:
patent: 5053700 (1991-10-01), Parrish
patent: 6229206 (2001-05-01), Schamberger et al.
Christopher P. Maiorana P.C.
LSI Logic Corporation
Thompson Craig
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