Static random access memory (SRAM)

Details Static random access memory (SRAM) Static random access memory (SRAM)

2000-06-23

2002-03-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189040

Reexamination Certificate

active

06356473

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to static random access memory (SRAM) circuits, and more particularly to approaches for reducing current consumption in SRAM circuits.
BACKGROUND OF THE INVENTION
Static random access memory (SRAM) circuits are highly valued in many applications due to their relatively fast access speeds. However, such fast access speeds typically come at the cost of increased current consumption and hence increased power consumption. With the advent of portable electronic devices, it has become an increasingly important goal to manufacture integrated circuits that consume less power. Thus, an increasingly important goal in SRAM circuit design has been to find ways to decrease the current and/or power consumption of such circuits, while maintaining relatively fast operating speeds.
SRAM circuits can typically include a number of SRAM memory cells. One particular type of SRAM memory cell is the six transistor (6-T) memory cell. One example of a 6-T memory cell is shown in FIG.
9
. The 6-T memory cell of
FIG. 9
is includes a pair of driver transistors Tr
1
and Tr
2
having cross-coupled gate-drain connections at nodes N
1
and N
2
. Access transistors Tr
3
and Tr
4
can connect nodes N
1
and N
2
to digit lines D and /D. A 6-T memory cell may further include a pair of load devices. In some configurations, load devices can include transistors, while in other configurations load devices can include resistors.
FIG. 9
illustrates an example of a 6-T memory cell with transistors Tr
5
and Tr
6
as load devices.
It is noted that while memory cells that include resistors as load devices are often referred to as “4-T” memory cells, to avoid confusion with “true” 4-T memory cells discussed in more depth below, such four transistor, two resistor-type memory cells will also be considered 6-T cells for the purposes of this discussion.
The gates of access transistors Tr
3
and Tr
4
can be connected to a word line WL. Load devices (Tr
5
and Tr
6
) can be connected between nodes N
1
and N
2
and a high power supply voltage. Driver transistors (Tr
1
and Tr
2
) can have source-drain paths connected between nodes N
1
and N
2
and a low power supply voltage.
SRAM circuits may select memory cells for access (e.g., a read or write operation) in a variety of ways. One type of access is provided by “true” asynchronous SRAM circuits. A true asynchronous SRAM circuit can operate in response to applied input signals, and not in response to an external timing signal, such as a periodic clock signal. In many applications, true asynchronous SRAM circuits timing is based on a transition in an applied address value.
An example of a true asynchronous SRAM circuit operation is shown in FIG.
10
.
FIG. 10
is a timing diagram showing an address value ADD, a chip select signal /CS, a write enable signal /WE, a data input value DIN, and an indication of selected word line values (SEL WL). In
FIG. 10
, a chip select signal /CS and write enable signal /WE can be active (low in this case) and the address can make a transition. A data value (DATA) that is to be written can also be entered.
In response to the address transition, a word line WL and digit line pair (D and /D) can be selected. The input data (DATA) may then be written into the memory cell selected by the word line and digit line pair (D and /D).
A drawback to such an arrangement is that a memory cell can remain selected while the write enable signal /WE is active. During such a time period, a current can flow through a digit line from a de-selected memory connected to the same word line. Such a current can contribute to overall current consumption in a SRAM circuit.
Another drawback to a conventional true asynchronous SRAM circuit is the timing constraints that may be presented by such circuits. In particular, a true asynchronous SRAM circuit that is undergoing a write operation to one address may undergo a subsequent transition to a second address. To prevent the write data from being erroneously written into the second address, a SRAM circuit may include a specification TWR that indicates a minimum time between the termination of a write enable (/WE) pulse and a subsequent address transition. Such a TWR specification is shown in
FIG. 10. A
TWR requirement may increase the overall time required to access an SRAM cell, thus decreasing the operating speed of the SRAM device.
A second type of asynchronous SRAM circuit can operate internally in a similar fashion to a synchronous SRAM devices. Namely, internal timing pulses can be generated to control read and/or write operations. However, unlike a synchronous SRAM circuit, such internal timing pulses are not generated in response to an externally applied periodic signal, but instead are generated in response to various transitions in other applied input signals. One such type of SRAM circuit can be referred to as a “pulse” word system. In a pulse word system, a memory cell can be selected at the particular time the read and write operations are taking place. More particularly, a pulse word system can generate timing pulses in response to transitions in address values and in response to transitions in write data values.
An example of a pulse word SRAM circuit operation is shown in FIG.
11
.
FIG. 11
is a timing diagram showing an address value ADD, a chip select signal /CS, a write enable signal /WE, a data input value DIN, and an indication of selected word line values (PW). In
FIG. 11
, a chip select signal /CS can be active (low in this case) while a write enable signal is inactive (high). In addition, the address can make a transition to a value A
0
. In response to the address transition, a pulse word signal (PULSE WL) can be activated, and data can be read from a memory cell corresponding to address A
0
.
Next, a write enable signal can be activated (transition low) while the chip select signal /CS is active (low) indicating a write operation. Further, an address can transition from an A
0
value to a value A
1
.
FIG. 11
particularly shows a “long” write operation where write data values may transition one or more times while a write enable signal is active. Consequently, a memory cell at address A
1
can be written to essentially multiple times.
In the above arrangement, because a memory cell is selected when the pulse word signal is active, the period of time during which a memory cell is selected can be less than that of a true asynchronous SRAM circuit. Consequently, current consumption can be reduced over a true asynchronous SRAM circuit approach.
Various examples of pulse word SRAM circuits are shown in Japanese Unexamined Patent Publication No. Hei 1-241089, Japanese Unexamined Patent Publication No. Hei 5-74162, and Japanese Unexamined Patent Publication No. Hei 8-222000.
However, as noted above, in a pulse word SRAM circuit a “long” write operation can take place. In a long write case, a pulse word signal (PW) can be generated for each transition in the write data. Consequently, the amount of time that a memory cell remains selected can be increased, essentially defeating the current saving features of a pulse word SRAM circuit. Still further, as the number of write data transitions increases, more current can be consumed.
It is further noted that a pulse word SRAM circuit may introduce time constraints between operations. More particularly, when a write operation occurs in a pulse SRAM, a precharge operation may be required before a subsequent read operation is performed. A precharge operation can precharge digit lines prior to a read operation. Thus, in a pulse word SRAM, reading may have to be postponed until after a precharge operation. This can reduce the overall operating speed of a pulse SRAM circuit.
While many conventional SRAM circuits include 6-T memory cells as previously described, in recent years a more compact memory cell has been proposed in an effort to provide higher density SRAM devices. The proposed memory cell is a “true” four transistor (4-T) memory cell. A true 4-T memory cell can omit the load devices (e.g., t

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