Television – Basic receiver with additional function – For display of additional information
Reexamination Certificate
1999-09-09
2002-03-12
Hsia, Sherrie (Department: 2614)
Television
Basic receiver with additional function
For display of additional information
C348S567000, C348S568000, C348S584000, C348S598000
Reexamination Certificate
active
06356314
ABSTRACT:
TECHNICAL FIELD
This invention relates to an image synthesizing device with which an NTSC or other such interlaced image can be synthesized and displayed in full, magnified, or reduced scale in any region of a VCA or other such non-interlaced image.
BACKGROUND ART
An interlaced image of the NTSC system, such as a CCD camera, has odd-numbered fields and even-numbered fields, and one frame (one screen) of image is made up of odd-numbered field images and even-numbered field images. Image scanning is performed alternately for the odd-numbered fields and even-numbered fields in field units, and one screen of image is displayed in two scans.
In contrast, with non-interlaced scanning such as VGA, there is no skipping as above, and one screen is displayed in a single scan, with the displayed image having less flicker than an interlaced scan.
Thus, since there are two different scanning methods for displaying, numerous techniques have been proposed in the past for converting interlaced signals into non-interlaced signals and displaying these in part of a non-interlaced display screen or over the entire region.
One such prior art is Japanese Patent Application Laid-Open No. 5-114026. With this prior art, there is a main image memory that holds main image data (non-interlaced signals), and a sub-image memory of the same capacity as the main image memory that stores sub-image data (interlaced signals) at an address corresponding to this frame memory. When part of the region of the sub-image stored in the sub-image memory is to be synthesized and displayed in part of the main image display region, the sub-image is read out from the sub-image memory when the scanning address of the sub-image memory becomes a specific address corresponding to the synthesis and display region, and when the scanning address of the main image becomes the address at which the sub-image is to be displayed, the display data outputted to the CRT display is switched to the sub-image data that has been read out from the main image data, thereby synthesizing the sub-image data on the main image screen.
Specifically, with this prior art, a sub-image memory of the same capacity as the main image memory capable of storing all sub-images is readied, and the data read-out timing from this sub-image memory is controlled so as to synthesize part of the sub-image on the main image display screen.
Because this prior art is thus provided with both a frame memory for storing main image data and an image memory for storing sub-image data of the same memory capacity as this frame memory, twice the frame memory capacity is required. Consequently, the memory mounting surface area is larger when the circuit is configured, making the overall device larger more expensive.
Another problem with this prior art is that when the sub-image is reduced or magnified in scale, the scale factor is restricted to powers of two, such as “1/2m” or “2m,” so the scale factor cannot be set in any way desired, which means that this approach is unsatisfactory when the goal is to reduce or magnify a sub-screen precisely to the desired size.
Also, with this prior art, the sub-image memory stores data by an address system in which the data for each pixel is in a one-to-one correspondence with the X-Y address of the CRT display device. Specifically, if the CRT display device is 640 dots wide by 480 dots high, and a one-dot image is one byte, then the sub-image data is stored in memory space as shown in FIG.
10
.
Since 640 dots of image data corresponds to 640 bytes, each horizontal synchronous scanning line corresponds to 640 bytes out of the 1024 bytes made up of the lower 10 bits of the memory address. Also, since 480 lines are required in the vertical direction, 480 of the upper 9 bits of the address (512) end up being allocated.
However, with a sub-image memory configured in this way, an area A occupied by the remaining 384 bytes for every horizontal synchronous scanning line of the 480 lines, and an area B occupied by the remaining 32 lines within the upper address space of the 512 lines are unused, so that a number of memories greater than the required memory capacity are required, which is disadvantageous in terms of both cost and mounting surface area.
The present invention was conceived in light of the above problems, and an object thereof is to provide an image synthesizing device with which the image data memory capacity needed for synthesis of main images and sub-images can be decreased, and the reduction or magnification scale factor of the sub-images can be set as desired.
Another object of the present invention is to provide an image conversion device and an image conversion method with which costs can be lowered by allowing non-interlaced signals to be converted into non-interlaced signals using a single frame memory.
Yet another object of the present invention is to provide an image synthesizing device with which costs can be lowered by allowing a specific extraction region of an interlaced scan sub-image to be synthesized and displayed in a specific display region on the display screen on which a non-interlaced scan main image is displayed, using a single serial access memory.
DISCLOSURE OF THE INVENTION
The first invention is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display, comprising: a frame memory that continuously stores, in an inputted order, only that data out of sub-image data that is within the display region P to be synthesized, and then reads out the stored sub-image data in the inputted order when a scanning address of the main image data is an address corresponding to the display region Q of the main image; and a selector that inputs the main image data displayed on the display and the sub-image data sequentially read out from the frame memory, and switches a selected channel from this main image data to the sub-image data and outputs it to the display, so that this sub-image data is displayed, when the scanning address of the main image data is an address corresponding to the display region Q of the main image.
Once the scanning address corresponds to the display region in which the sub-image is to be synthesized at the time of sub-image input, the sub-image data is written continuously to the frame memory in the order in which it was inputted, after which the sub-image data is continuously read out from the frame memory in this input order corresponding to the display address when the main image data is displayed in the region Q where the main image is synthesized and displayed, and the main image data is switched to this read sub-image data and displayed on the display, which results in the sub-image being displayed in full scale. In this case, the sub-image may be either interlaced or non-interlaced. Thus, with this invention of claim
1
, the sub-images are stored in the continuous address space of the frame memory, so the capacity of the frame memory can be decreased.
The second invention is an image synthesizing device with which a specific display region P of a sub-image is synthesized and displayed within a specific display region Q of a main image displayed on a display, comprising: a first frame memory that continuously stores, in an inputted order, data of odd-numbered fields within the display region P to be synthesized out of interlaced sub-image data, and then reads out the stored sub-image data in the inputted order when a scanning address of the main image data is an address of an odd-numbered line corresponding to the display region Q of the main image; a second frame memory that continuously stores, in the inputted order, data of even-numbered fields within the display region P to be synthesized out of the interlaced sub-image data, and then reads out the stored sub-image data in the inputted order when the scanning address of the main image data is an address of an even-numbered line corresponding to the display region Q of the main image; and a selector that inputs the
Hsia Sherrie
Komatsu Ltd.
Varndell & Varndell PLLC
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