Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2001-03-08
2002-05-07
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C365S201000
Reexamination Certificate
active
06384665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the disabling of signal lines. More particularly, the present invention relates to the use of programmable soft fuses for disabling address lines in an array of random access memory (RAM).
2. The Prior Art
The problems associated with the failure of individual memory cells in a RAM cell array are well known in the art. During the fabrication stage, when a failure is detected in a memory cell, the row that contains the defect must be disabled. One method known in the art of disabling a row of memory is to use a hard fuse. A hard fuse is a miniature fuse fabricated from metal and disposed on the silicon. When it is desired to disable a particular row of memory, the fuse is severed, typically with a laser.
FIG. 1
shows a prior art system incorporating a RAM cell array with hard fuses.
FIG. 1
shows address line
10
coupling address information into address decoder
20
. Address decoder
20
then properly directs that address information along address line
30
into RAM cell array
40
. RAM cell array
40
is shown with the prior art hard fuses located in a corner of array
40
in area
50
.
The use of hard fuses to disable defective rows of memory has certain disadvantages. For example, because of the destructive nature of the laser cutting, the hard fuses must be located away from other sensitive parts on the chip, thus necessitating a larger design footprint.
Further disadvantages resulting from the use of hard fuses can be seen by referring to
FIG. 2
, which shows a conceptual detail of array
40
and hard fuse area
50
.
In a typical operation, a test will be performed on array
40
to verify its integrity prior to sale. A typical array of memory is formed by various row lines
41
and column lines
42
. The intersection of these lines forms a memory location
43
. In a typical test, each of the many memory locations that comprises a typical memory cell like memory location
43
are cycled through by storing and retrieving data through address line
30
. If a defective location is detected, a corresponding hard fuse F
1
is severed, rendering the bad location inoperable. Once the test is complete, the finished RAM cell array is then sealed, packaged and cannot be modified.
The critical path of column line
42
is longer that would be necessary if hard fuse F
1
was not present. In high speed, high density, micro-electronics, the distance critical signals must travel is of great concern, and short signal paths are desired. Hence, any unnecessary signal path length resulting from the use of hard fuses is a great disadvantage. As is readily apparent, there is a need for a method for disabling defective memory cells that minimizes critical signal paths.
An additional disadvantage is created by the permanency of the hard fuse operation. As mentioned above, after the RAM cell array is tested, it is sealed. As a consequence, if there are further failures after the sealing of the array, the entire array must be scrapped. Thus, there is a need for a fusing method that allows for the detection and elimination of defective memory cell arrays in the field.
The present invention satisfies the foregoing needs through the use of a programmable soft fuse. With a soft fuse, a row of memory containing a defective memory cell may be deactivated using electronic means rather than destructive lasers.
SUMMARY OF THE INVENTION
The present invention relates to the use of a programmable soft fuse for disabling a signal line. A preferred embodiment has the following elements: an electronic switching circuit having an input, an output, and at least one trigger input, a latch coupled to the switching circuit, a control circuit coupled to the latch, and a reset circuit coupled to the latch. In another preferred embodiment of the present invention, a precharge device is included and coupled to the switch and latch.
A method of disabling a data line using a soft fuse is disclosed, including providing a soft fuse having a control means, providing a memory array having a plurality of address lines, providing an address decoder, connecting the soft fuse between the address decoder and the memory array, testing the memory array, locating a bad address line in the array, entering the location of the bad address line into the address decoder, and strobing the control means, causing the programmable fuse to turn off, thus disabling the defective memory cell.
An alternate method is disclosed, which further includes: providing shifting circuitry, connecting the shifting circuitry to the address decoder, the soft fuse circuitry, and the memory array accepting data from the address decoder into the shifting circuitry, and providing the data to a predetermined row in the memory array.
REFERENCES:
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IEEE Journal of Solid-State Circuits, vol. 31, No. 3, Mar. 1996, “A Scalable Pipelined Architecture for Fast Buffer SRAM's”, C.J. Nicol and A. G. Dickinson, pp 419-429.
IEEE Journal of Solid-State Circuits, vol. 26, No. 1, Jan. 1991, “A Flexible Redundancy Technique for High-Density DRAM's” M. Horiguchi, J. Etoh, M. Aoki, K. Itoh, and T. Matsumoto, pp. 12-17.
Callahan Timothy P.
Nguyen Hai L.
Sierra Patent Group Ltd.
Sun Microsystems Inc.
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