Semiconductor laser device

Details Semiconductor laser device Semiconductor laser device

2001-04-09

2002-07-02

Ip, Paul (Department: 2828)

Coherent light generators

Particular active media

Semiconductor

C372S043010, C372S044010, C372S045013, C372S046012, C372S049010, C372S049010, C372S049010, C372S050121

Reexamination Certificate

active

06414977

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor laser device and a manufacturing method thereof. In particular, it relates to a semiconductor laser device used to process optical information and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor laser device for optical information processing has conventionally employed a gain guided structure using a GaAs current blocking layer. Recently, there has been, however, developed a semiconductor laser device which employs a real refractive index guided structure using an AlInP layer as a current blocking layer to reduce an operating current.
A real refractive index guided structure may reduce an optical absorption loss in a current blocking layer resulting in not only a reduced threshold current but also an improved luminous efficiency, therefore a reduced operating current.
This technical trend has been driven for developing semiconductor laser device shaving a higher output. Conventional optical information processing involves only reading as in, for example, DVD-ROM, which does not require very high output. Recent optical information processing involves, however, not simply reading but also writing on a recording medium as in, for example, DVD-RW or DVD-R, which necessarily requires a higher output. It has been, therefore, required that an internal loss is minimized to reduce an operating current for improving temperature properties of the semiconductor laser device and thus reliability under a high output.
FIG. 14
is a cross-sectional view of a conventional SAS (Self-Aligned Structure) type of red semiconductor laser diode (hereinafter, referred to as a “red LD”) described in Electronics Letters, Vol. 33, No. 14 (1997), pp.1223-5.
In
FIG. 14
, reference numeral
100
denotes a red LD,
102
an n-type GaAs substrate (hereinafter, n-type and p-type are denoted as “n-” and “p-”, respectively),
104
an n-GaAs buffer layer,
106
a lower clad layer made of n-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P, and
108
an active layer of an MQW structure made of GaInP/AlGaInP where GaInP is a material for a well layer and AlGaInP is a material for a barrier layer.
In this figure, reference numeral
110
denotes a first upper clad layer made of p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P,
112
a current blocking layer made of n-AlInP,
114
a stripe-shaped opening to be a current channel in the current blocking layer
112
,
116
a second upper clad layer made of p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P,
118
a p-GaAs contact layer,
120
a p-electrode, and
122
an n-electrode.
There will be described a process for manufacturing this semiconductor laser device
100
.
FIGS. 15
,
16
and
17
are cross-sectional views of a conventional red LD in individual manufacturing steps.
First, on an n-GaAs substrate
102
are sequentially deposited an n-GaAs layer to be a buffer layer
104
, an n-(Al
0.7
Ga
0.3
)
0.5
In
0.5
layer to be a lower clad layer
106
, a GaInP/AlGaInP MQW layer to be an active layer
108
, a p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer to be a first upper clad layer
110
and an n-AlInP layer to be a current blocking layer
112
, by primary epitaxial growth based on crystal growth such as MOCVD. For dopants, silicon is used as an n-type dopant while zinc is used as a p-type dopant. The result of this step is shown in FIG.
15
.
Then, a resist pattern
126
is formed on the surface of the n-AlInp layer to be a current blocking layer
112
by a photolithographic process, and a stripe-shaped opening
114
to be a current path is formed in the n-AlInP layer to be the current blocking layer
112
by wet etching. The result of this step is shown in FIG.
16
.
After removing the resist pattern
126
, a p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer to be a second upper clad layer
116
is formed on the p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer to be a first upper clad layer
110
facing the opening
114
and the n-AlInP layer to be a current blocking layer
112
by secondary epitaxial growth based on crystal growth such as MOCVD. The result of this step is shown in FIG.
17
.
Then, a p-GaAs layer to be a contact layer
118
is formed on the p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
layer to be a second upper clad layer
116
.
In this process, crystal growth temperature is about 650° C. to 750° C. A crystal growth temperature as low as possible is used to prevent the p-type dopant, Zn, from diffusing from the p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer, as the first upper clad layer
110
, into the MQW layer, the active layer
108
, to the maximum extent possible.
Then, a p-electrode
120
and an n-electrode
122
are formed on the surface of the p-GaAs layer to be a contact layer I
10
and on the rear surface of the n-GaAs substrate
102
, respectively.
A conventional red LD
100
has a configuration as described above. When forming the p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer for the second upper clad layer
116
on the n-AlInP layer for the current blocking layer
112
in the manufacturing process for the red LD
100
as illustrated in
FIG. 17
, lattice defects frequently develop on the surface facing the opening
114
in the n-AlInP layer for the current blocking layer
112
, leading to an increase in internal loss of light, deterioration in temperature properties, and poor reliability of the red LD
100
.
A technique for preventing lattice defects in crystal growth has been described in Proceedings of the Tenth International Conference on Metal organic Vapor Phase Epitaxy (2000), p. 82. In the report, an (Al
0.7
Ga
0.3
)
0.51
In
0.49
P layer is deposited on a GaAs substrate which is a (
100
) facet misoriented by 10° toward [011] direction. Then, on the layer is formed an Al
0.51
In
0.49
P layer having a grooved structure whose side wall is a (
111
) A facet, and with Ga
0.51
In
0.49
P as a marker sandwiched in between, an (Al
0.7
Ga
0.3
)
0.51
In
0.49
P layer is formed above the (Al
0.7
Ga
0.3
)
0.51
In
0.49
P layer parallel to the GaAs substrate exposed in the bottom of the grooved structure and above the Al
0.51
In
0.49
P layer having a (
111
) A facet, during which development of lattice defects is studied using the then substrate temperature as a parameter.
According to the report, crystal growth was caused at substrate temperatures of 720° C., 760° C. and 800° C. It was found that lattice defects developed in a crystal layer growing on a (
111
) A facet at a substrate temperature of 720° C. or 760° C., while crystal growth at a substrate temperature of 800° C. reduced lattice defects in the (Al
0.7
Ga
0.3
)
0.51
In
0.49
P layer on a (
111
) A facet.
However, for a red LD, a crystal growth temperature of 800° C. may cause diffusion of the p-type dopant Zn from the p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer as a first upper clad layer
110
to the MQW layer to be an active layer
108
, leading to deterioration in temperature properties or reliability in current-optical output performance.
Besides the prior art described above, JP-B 2842465 has disclosed an SAS type semiconductor laser where on the surface of a current blocking layer made of AlGaAs material having a stripe-shaped opening is deposited a protective layer made of an AlGaAs material with small aluminum content, on which a p-AlGaAs material is deposited as a p-clad layer, but has not described that on a current blocking layer made of an AlInP material are formed a capping layer made of a GaInP material and a p-(Al
0.7
Ga
0.3
)
0.5
In
0.5
P layer.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problem in the art, and an objective of this invention is to provide a reliable semiconductor laser device exhibiting a reduced threshold current with less deterioration in temperature properties in current-optical output performance.
A semiconductor laser device according to the present invention comprises: a semiconductor substrate of a first conductivity type; a first clad layer of a first conductivity type made of a III-V group compound semiconductor disposed on the semiconductor substrate; an active layer made of a III-V

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