Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-03-14
2002-07-02
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S540000
Reexamination Certificate
active
06414535
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device for generating an internal operational factor corresponding to an external operational factor such as a power supply voltage or a clock signal. More specifically, the present invention relates to a semiconductor device including a phase locked loop (PLL) circuit or a delay locked loop (DLL) circuit or a ring oscillator for generating an internal clock signal and/or a semiconductor device including a down converter for generating an internal power supply potential by down-converting level of an externally applied power supply potential.
2. Description of the Background Art
A PLL circuit has been known as a circuit for generating an internal signal which is in phase/frequency synchronization with an externally applied signal. The PLL circuit is used for reproducing color subcarrier for synchronous detection of a color burst signal in an integrated circuit for reproducing an ATC (Automatic Control) type color subcarrier, for improving stability of color reproduction in a color television. It is also used in the field of wire communication for synchronizing a clock output from a highly stable oscillator arranged in one station with a reference clock received from a high level station so as to distribute stable clock to various communication devices in the station.
FIG. 1
shows a schematic structure of a conventional PLL. Referring to
FIG. 1
, the PLL circuit includes a phase comparator circuit
2
receiving an internal clock intCLK and an external clock extCLK for outputting control signals UP and /DOWN corresponding to frequency and phase deviation between the internal clock intCLK and the external clock extCLK; a charge pump circuit
3
for adjusting potential level of its output node
3
a
in accordance with the control signals UP and /DOWN from phase comparator circuit
2
; a loop filter
4
for filtering the output signal (potential) from output node
3
a
of charge pump circuit
3
; a current adjusting potential output circuit
5
receiving the output potential VP from loop filter
4
for outputting an output potential VN corresponding to the output potential VP; and a ring oscillator having its oscillation frequency controlled in accordance with the output potential VP from loop filter
4
and the potential VN from current adjusting potential output circuit
5
. The internal clock intCLK is output from ring oscillator
6
.
Phase comparator
2
has a structure of a phase frequency comparator (PFC) and it sets the control signal UP at an L (low) level when the frequency of the internal clock intCLK is larger than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is in advance of the phase of the external clock extCLK, and it sets the control signal UP at an H (high) level when the frequency of the internal clock intCLK is smaller than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is lagged from that of the external clock extCLK. The control signal /DOWN from the phase comparator circuit
2
is set to the L level when the frequency of the internal clock intCLK is larger than the frequency of external clock extCLK or the phase of internal clock intCLK is in advance of the phase of the external clock extCLK, and it is set to the H level when the frequency of the internal clock intCLK is smaller than the frequency of the external clock extCLK or when the phase of the internal clock intCLK is lagged from the phase of the external clock extCLK. The phase comparator circuit
2
operates as a frequency error detector automatically when unlocked, and operates as a phase difference detector in a capture range.
Charge pump circuit
3
includes a constant current circuit
3
c
connected between a power supply node
1
a
to which the power supply potential VCC is applied and a node
3
b,
for supplying a constant current to node
3
b;
a p channel MOS (insulated gate type field effect) transistor
3
d
connected between node
3
b
and an output node
2
a
and receiving at its gate the control signal UP from phase comparator circuit; an n channel MOS transistor
3
f
connected between output node
3
a
and a node
3
e
and receiving at its gate the control signal /DOWN from phase comparator circuit
2
; and a constant current circuit
3
g
connected between node
3
e
and a ground node
1
b
receiving the ground potential GND for sinking a prescribed constant current. When control signal UP is at the L level and the control signal /DOWN is at the L level, charge pump circuit
3
supplies charges to node
3
g,
and when control signal UP is at the H level and the control signal /DOWN is at the H level, it sinks charges from node
3
a.
Loop filter
4
serves as a lowpass filter for removing a high frequency component of potential change at the output node
3
a
of charge pump circuit
3
. Loop filter
4
includes a resistance element
4
b
connected between output node
3
a
and node
4
a;
a resistance element
4
d
connected between nodes
4
a
and
4
c;
and a capacitor
4
e
connected between node
4
c
and the ground node
1
b.
Resistance elements
4
b
and
4
d
and the capacitor
4
e
constitute an RC lowpass filter, and a potential VP corresponding to the potential on output node
3
a
of charge pump circuit
3
is output from node
4
a.
Current adjusting potential output circuit
5
includes a p channel MOS transistor
5
b
connected between power supply node
1
a
and node
5
a
and having its gate connected to node
4
a
of loop filter
4
; and an n channel MOS transistor
5
c
connected between node
5
a
and ground node
1
b
and having its gate connected to node
5
a.
The n channel MOS transistor
5
c
has its gate and drain connected to each other and operates in a saturation region, and therefore it sets the potential at gate
5
a
in accordance with a current applied from p channel MOS transistor
5
b,
in accordance with square-law characteristic of (Ids=&bgr;(Vgs−Vth)
2
).
Ring oscillator
6
includes an odd-number of inverters
6
a
connected in a ring shape, each having driving current (operational current) adjusted in accordance with output potentials VP and VN. These odd-number of inverters
6
a
have the same structure and denoted by the same reference character. Inverter
6
a
includes a current adjusting p channel MOS transistor
6
ab
connected between power supply node
1
a
and a node
6
aa
and receiving at its gate the output potential VP from loop filter
4
; a p channel MOS transistor
6
ae
connected between node
6
aa
and an output node
6
ac
and having its gate connected to input node
6
ad;
an n channel MOS transistor
6
ad
connected between output node
6
ac
and a node
6
af
and having its gate connected to input node
6
ad;
and a current adjusting n channel MOS transistor
6
ah
connected between node
6
af
and ground node
1
b
and receiving at its gate the output potential VN from current adjusting potential output circuit
5
. The operation will be briefly described.
When the frequency of the internal clock intCLK is larger than the frequency of external clock extCLK or when the phase of the internal clock intCLK is in advance of the phase of the external clock extCLK, phase comparator circuit
2
sets control signals UP and /DOWN both to the L level. In this state, p channel MOS transistor
3
d
in charge pump circuit
3
is rendered conductive and n channel MOS transistor
3
f
is rendered non-conductive. Charges are supplied to output node
3
a
through p channel MOS transistor
3
d
which is conductive, the potential at output node
3
a
rises, and in response, output potential VP at node
4
a
of loop filter
4
increases. As the output potential VP increases, conductance of p channel MOS transistor
5
b
in current adjusting potential output circuit
5
becomes smaller, and current flowing therethrough becomes smaller. As the amount of current from MOS transistor
5
b
becomes smaller, output potential VN at node
5
a
lowers
Cunningham Terry D.
Luu An T.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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