Semiconductor device

Details Semiconductor device Semiconductor device

2000-03-20

2002-01-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06335901

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the technology of semiconductor devices, and particularly to a semiconductor device which is suitable for an SDRAM (Synchronous Dynamic Random Access Memory) which can be switched to perform a SDR (Single Data Rate) operation and a DDR (Double Data Rate) operation.
Synchronous memories such as SDRAMs have their operational timing controlled based on an external clock signal such as a system clock signal supplied from the outside. Synchronous memories of this type are characterized by relatively easy treatment of the internal operational timing by use of the external clock signal and the ability to achieve relatively fast operation.
SDRAMs are known which perform SDR type operations, in which data input/output is timed to the rising edge of the external clock signal, and DDR type operations, in which data input/output is timed to both the rising and falling edges of the external clock signal.
SUMMARY OF THE INVENTION
SDRAMs of the SDR type can operate relatively fast and can be used easily for general electronic systems which operate under control of a clock signal. Specifically, the relation between data input/output and the external clock signal, i.e., data input/output timed to the rising edge of the external clock signal, of the SDR-type SDRAM is fairly analogous to the operation of general electronic systems, in which operations are timed to the rising or falling edge or the transition from a low level to a high level (or from high to low) of the clock signal, or, in other words, it is analogous to the relation between the clock signal and the signal to be transferred in general electronic systems which operate by being timed to the leading edge or trailing edge of a clock signal.
In contrast, SDRAMs of the DDR type operate for data input/output by being timed to the rising and falling edges of a clock signal. Although DDR-type SDRAMs involve application electronic systems having some intricate timing design, these SDRAMs perform twice the data input/output operations per unit time as SDR-type SDRAMs at the same clock frequency. Namely, DDR-type SDRAMs are capable of faster data access.
SDRAMs of the SDR type and DDR type have similar characteristics such as the introduction of external control signals and command signals in synchronism with the external clock signal, the address input operation, and the data input/output operation, and have like circuit arrangements of the memory cell matrix and associated address selection circuit and the peripheral circuits such as the sense amplifiers and main amplifiers.
The inventors of the present invention have studied the design of a uniform semiconductor chip which can be employed both as an SDR-spec SDRAM and a DDR-spec SDRAM by switching. Accomplishing this semiconductor chip design enables the common use of photolithography masks for fabricating both SDR-spec and DDR-spec SDRAMs and the implementation of a common fabrication process and a common test process for both SDRAMS. As a result, the reduction of manufacturing cost can be expected.
Another expectation, which is derived from the configuration of any of the SDR-spec and DDR-spec SDRAMs embodied in a uniform semiconductor chip, is the potential capability to meet an increased demand of any type of SDRAMS.
In the course of the in-depth studies on the designing of SDR-spec and DDR-spec SDRAMs embodied in a uniform semiconductor chip, the inventors of the present invention have found the presence of the following problems to be solved.
(1) Problem on the Internal Clock System
It is necessary for the internal circuits of an SDRAM to be operative by being timed to both the rising edge and falling edge of the external clock signal so that the SDRAM can operate in the DDR mode. In this case, for controlling the internal circuits to operate in response to the rising and falling edges of the external clock signal, it is desired to generate an internal clock signal which is timed to both the rising and falling edges of the external clock signal, i.e., transitions from one level to another timed to the rising edge and falling edge of the external clock signal, so that the internal circuits operate in response to the rising and falling edges of the external clock signal.
Clock-based componential circuits, such as the input buffer, which operate in response to the external clock signal have inevitably a time lag or phase shift of the output signal relative to the input signal. Regardless of this inevitable output delay of componential circuits which base their operation on the external clock signal, it is desirable for the internal clock signal to have a reduced phase shift relative to the external clock signal. Another crucial design factor in the case of the relatively fast operation in the DDR mode is the generation of an internal clock signal in consideration of the operation delay of the internal circuits. It is desired to connect the semiconductor device to an external device such as a memory controller or microprocessor in a proper timing relation with the external clock signal regardless of the operation delay in the internal circuits. More desirable operation of the semiconductor device is made possible by providing an internal clock signal which has a leading phase relative to the external clock signal to a sufficient extent to compensate for the operation delay of the internal circuits. In order to produce an internal clock signal with a proper phase relation regardless of the operation delay and phase shift of the componential circuits, a clock regenerating circuit provided in the SDRAM for producing the internal clock signal from the external clock signal is designed to use the functions of signal phase judgement and adjustment, called DLL (delayed lock loop), PLL (phase-locked loop) and SMD (synchronous mirror delay), and to use the known circuit technique of signal phase control for producing a signal which is synchronized and phase-controlled to the input signal.
The clock-based circuit which produces an internal clock signal from the external clock signal for the device operation in SDR operation (or SDR mode or SDR specification) can conceivably be shared with the circuit for the DDR operation to achieve simplification of the whole uniform semiconductor chip. Nevertheless, these circuits are desirably separate from the clock-based circuit for the DDR operation under the following technical considerations.
Signals such as system clock signals produced in electronic systems are not necessarily designed to have a constant period and constant phase. Instead, it is even desirable for some electronic systems to have their clock period changed periodically. For example, in an electronic system operating based on a clock signal, a change of operation current of a clock-based circuit often produces a noise of a relatively large level. In case the clock period is changed periodically, noises attributable to the clock signal have their frequency spectrum dispersed by the alteration of the clock period, resulting in a reduced noise level at certain frequencies. For the effective dispersion of the noise frequency spectrum, it is desirable to change the clock period in a short interval, such as in every one or several clock cycles.
On the other hand, the above-mentioned circuit technique of signal phase control generally necessitates multiple clock cycles for phase control, and therefore it is not easily responsive to fast changing clock periods intended for the dispersion of the noise frequency spectrum. On this account, it should be a primary aim for the DDR mode to produce a fast clock signal from the external clock signal. In contrast, for the SDR mode, the internal clock signal virtually corresponds with the external clock signal, and it is desirably highly responsive to changing periods of the external clock signal.
Therefore, it is desirable to design separate clock-based circuits for the SDR mode and DDR mode.
(2) Problem on the Data Transfer Line
In the SDR-spec SDRAM, there are states in which read-out data an

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