Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
1998-12-30
2002-09-24
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S125000, C438S126000, C438S127000, C029S827000, C029S841000, C029S856000, C257S783000, C257S787000
Reexamination Certificate
active
06455354
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a “chip-on-board” (COB) semiconductor assembly and, more particularly, to a method and apparatus for reducing stress resulting from lodging of filler particles present in encapsulant and glob top materials between a surface of a semiconductor die and a corresponding surface of a semiconductor substrate and for visual inspection of the attachment of the semiconductor die to the semiconductor substrate with the use of tape attachment material.
2. State of the Art
Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
COB—Chip-On-Board: The techniques used to attach a semiconductor die to a semiconductor substrate, such as a printed circuit board.
Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die or portion thereof in a COB assembly.
Wire Bonding: Conductive wires attached between a semiconductor die and a circuit board or leadframe to form an electrical connection therebetween.
TAB—Tape Automated Bonding: Conductive traces are formed on a dielectric film such as a polyimide (the structure also being termed a “flex circuit”), and the film is precisely placed to electrically connect a semiconductor die and a circuit board or leadframe through the conductive traces. Multiple connections are simultaneously effected.
FIGS. 14 and 15
illustrate exemplary COB assemblies
200
each comprising a semiconductor die
202
back-bonded with an adhesive layer
204
to a semiconductor substrate
206
. The semiconductor die
202
is in electrical communication with the semiconductor substrate
206
through electrical elements extending between bond pads
208
on the semiconductor die
202
and traces
212
on the semiconductor substrate
206
. The electrical elements are generally bond wires
214
, as illustrated in
FIG. 14
, or TAB connections
216
, as illustrated in FIG.
15
.
In wire bonding, as illustrated in
FIG. 14
, a plurality of bond wires
214
is attached, one at a time, to each bond pad
208
on the semiconductor die
202
and extends to a corresponding lead or trace
212
on the semiconductor substrate
206
. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts.
With TAB, as illustrated in
FIG. 15
, TAB connectors
216
(generally metal leads carried on an insulating tape, such as a polyimide) are attached to each bond pad
208
on the semiconductor die
202
and to a corresponding lead or trace
212
on the semiconductor substrate
206
.
An encapsulant
218
, such as a plastic resin, is generally used to cover the bond wires
214
(
FIG. 14
) and TAB connectors
216
(
FIG. 15
) to prevent contamination, aid mechanical attachment of the assembly components, and increase long-term reliability of the electronics with reasonably low-cost materials.
An exemplary technique of forming the encapsulant
218
is molding and, more specifically, transfer molding. In the transfer molding process (and with specific reference to COB die assemblies), after the semiconductor die
202
is attached to the semiconductor substrate
206
(e.g., FR-4 printed circuit board) and electrical connections made (by wire bonding or TAB) to form a die assembly, the die assembly is placed in a mold cavity in a transfer molding machine. The die assembly is thereafter encapsulated in a thermosetting polymer which, when heated, reacts irreversibly to form a highly cross-linked matrix no longer capable of being re-melted. Additionally, another common manner of forming encapsulants for COB assemblages is “glob top” polymeric encapsulation. Glob top encapsulation can be applied by dispensing suitably degassed material from a reservoir through a needle-like nozzle onto the die assembly.
The thermosetting polymer of transfer molding generally is comprised of three major components: an epoxy resin, a hardener (including accelerators), and a filler material. Other additives such as flame retardants, mold release agents and colorants are also employed in relatively small amounts. Furthermore, glob top encapsulation can comprise a non-linear thixotropic material that also includes fillers to achieve the desired degree of thixotropy.
While many variations of the three major components are known in the art, the present invention focuses on the filler materials employed and their effects on the active semiconductor die surfaces and corresponding semiconductor substrate surfaces.
Filler materials are usually a form of fused silica, although other materials such as calcium carbonates, calcium silicates, talc, mica and clays have been employed for less rigorous applications. Powdered fused quartz is currently the primary filler used in encapsulants. Fillers provide a number of advantages in comparison to unfilled encapsulants. For example, fillers reinforce the polymer and thus provide additional package strength, enhance thermal conductivity of the package, provide enhanced resistance to thermal shock, and greatly reduce the cost of the polymer in comparison to its unfilled state. Fillers also beneficially reduce the coefficient of thermal expansion (CTE) of the composite material by about fifty percent in comparison to the unfilled polymer, resulting in a CTE much closer to that of the silicon or gallium arsenide die. Filler materials, however, also present some recognized disadvantages, including increasing the stiffness of the plastic package, as well as the moisture permeability of the package.
Two problems encountered in transfer molding are bond wire sweep and connection detachment. Bond wire sweep occurs in wire bonded packages wherein the encapsulant material, which is injected into the mold under pressure, deforms the bond wires which can cause shorting. Connection detachment can occur in either TAB connections
216
or bond wires
214
, wherein stresses created by the pressurized encapsulant material result in the detachment of the TAB connections
216
or bond wires
214
from either the bond pad
208
or the trace
212
.
To alleviate this problem and to reduce the thickness of the semiconductor assembly, as illustrated in
FIG. 16
, a technique of face-down attachment of a semiconductor die
232
onto a semiconductor substrate
234
with an adhesive tape
236
has been developed. With this technique, the semiconductor substrate
234
has an opening
238
therethrough with electrical connections
240
(shown as bond wires) extending through the opening
238
to connect the bond pads
242
on an active surface
262
of the semiconductor die
232
to the traces
244
on an active surface
250
of the semiconductor substrate
234
. The adhesive tape
236
used in these assemblies is generally narrow and does not extend to an edge
246
of the semiconductor die
232
, resulting in exterior voids
248
, and does not extend to an edge
252
of the opening
238
, resulting in interior voids
254
. The opening
238
is filled and the electrical connections
240
are covered with a glob top material
256
injected into the opening
238
, as shown in FIG.
17
. Thus, the electrical connections
240
are protected from bond wire sweep and connection detachment. As shown in
FIG. 18
, an encapsulant material
258
is molded over the semiconductor die
232
.
Unfortunately, a significant disadvantage of using glob top materials and encapsulant materials having filler particles is the potential for damage to the active surface
262
of the semiconductor die
232
and/or a back surface
264
of the semiconductor substrate
234
resulting from the lodging or wedging of filler particles
266
between the semiconductor die active surface
262
a
Chambliss Alonzo
Micro)n Technology, Inc.
Talbott David L.
TraskBritt
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