Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-08-15
2002-09-24
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S754000, C257S773000
Reexamination Certificate
active
06455942
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a plurality of metal lines each of which partially straps a different one of a plurality of polysilicon lines in a semiconductor integrated circuit device.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit devices are well known in the art. In particular, in the field of memory devices, including both volatile (such as DRAM or SRAM) as well as nonvolatile (such as FLASH), a plurality of polysilicon lines are used as row lines to access various memory cells. Because these row lines are made out of polysilicon, they tend to have higher resistivity than conductors made out of metal. Thus, metal lines are used to “strap” various polysilicon lines. By strapping it is meant to connect a metal line in parallel with the polysilicon row line to reduce the resistivity of the polysilicon row line.
As the scale of integration increases, i.e., the smallest dimension of a feature in a semiconductor integrated circuit device decreases, the width of the polysilicon lines will also decrease. However, the scale of integration for metal lines has not kept pace at the same rate as the scale of integration for other features such as the polysilicon lines. In other words, the width of the metal strapping lines has not been reduced at the same rate as the width of the polysilicon lines.
Thus, a metal line having a width greater than a plurality of polysilicon lines, may be segmented into a plurality of metal segments with each metal segment used to strap a different one of the polysilicon lines. The present invention deals with the optimal position for the strapping of such a partial strapped polysilicon line.
SUMMARY OF THE INVENTION
In the present invention, a semiconductor integrated circuit device comprises a semiconductor substrate with a plurality of circuits therein. A plurality of substantially parallel, laterally adjacent spaced apart polysilicon lines are insulated from the substrate and interconnect the plurality of circuits. Each of the plurality of polysilicon lines has a first end and a second end and has substantially the same length between the first end and the second end with electrical signals traversing from the second end to the first end. A plurality of substantially collinear metal lines are spaced apart from the plurality of polysilicon lines. Each of the plurality of metal lines electrically connects to a different one of the plurality of polysilicon lines. The metal lines are arranged from the first end to the second end with each metal line having a length of
X
=
L
n
+
1
/
3
.
The metal line at the second end has a length of {fraction (4/3)}x where L is the length between the first end and the second end and n is the number of metal lines.
REFERENCES:
patent: 5933725 (1999-08-01), Kirsch et al.
patent: 6243311 (2001-06-01), Keeth
patent: 08330536 (1996-12-01), None
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
Wilson Allan R.
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