Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-27
2002-03-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270
Reexamination Certificate
active
06363012
ABSTRACT:
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the operation of a “flash” electrically-erasable programmable read only memory (“Flash EEPROM”) cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as micro controllers, microprocessors, application specific integrated circuits, embedded memory applications, among others.
Industry has used or proposed a variety of memory devices. An example of such a memory device is an erasable programmable read-only memory (“EPROM”) device. The EPROM device is readable, writeable, and erasable, i.e., programmable. The EPROM is implemented using a floating gate field effect transistor, which has certain binary states. That is, a binary state is represented by the presence or absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
A wide variety of EPROMs is available. In a traditional form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (“UVEPROMs”). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate where charge is accumulated.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM” or “E
2
PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
The programming of flash memory cells typically takes at least a few micro seconds, which is slow when compared to some memory cells which operate at hundreds of times faster speed. This relatively slow programming speed of the flash memory cells is particularly problematic in a large recording devices, such as, voice or digital image recording devices, that uses flash EEPROM memories. Therefore, improvement in the programming speed of the flash memory cells is desirable.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and device for operating a flash memory cell is provided. In an exemplary embodiment, the present invention provides a method of programming a flash memory device that enhances programming efficiency using a hot carrier injection process.
In a specific embodiment, the present invention provides a method of operating a flash memory structure including a programming step. The method includes providing a flash memory device. The flash memory device has a substrate of first conductivity type, a source region of second conductivity type defined in the substrate and a drain region of second conductivity type defined in the substrate. The flash memory device can be a split gate, a stacked gate, or other type of physical structure. The method includes applying a drain voltage of a first polarity type ranging from about 4 to about 12 volts on the drain region and applying a control gate voltage of first polarity type ranging from about 1.5 to about 2 volts on a control gate. The method also includes applying a source voltage of second polarity type ranging from about −0.2 volt to about −0.5 volt on the source region, while maintaining a ground potential on the substrate to inject electrons onto a floating gate, which is coupled to the control gate, to program the floating gate to a logic state.
In an alternative embodiment, the present invention provides a method of programming a flash memory structure. The method includes providing a flash memory device. The flash memory device has a substrate of second conductivity type and a well of first conductivity type region defined in the substrate of second conductivity type. A drain region of second conductivity type is defined in the well region and a source region of second conductivity type is defined in the well region. Selected voltages are applied to program the device. Here, the method includes applying a drain voltage of first polarity type ranging from about 4 to about 12 volts on the drain region and applying a control gate voltage of first polarity type ranging from about 1.5 to about 10 volts on a control gate.
In a further embodiment, the present invention provides a method for programming a flash memory device in a memory array. The memory array comprises a plurality of flash memory devices, each of the devices is coupled to a column address decoder and a row address decoder. Each of the devices also coupled to a source bias line, which is coupled to a bias potential generation circuit. The bias potential generation circuit is coupled to the source bias line through a logic circuit. Each flash memory device includes a substrate of first conductivity type, a source region of second conductivity type defined in the substrate and a drain region of second conductivity type defined in the substrate. The method comprises selectively applying a drain voltage of first polarity type ranging from about 4 to about 12 volts on the drain region and applying a control gate voltage of first polarity type ranging from about 1.5 to about 2 volts on a control gate of at least one of the flash memory devices. A source voltage of second polarity type ranging from about 0.2 volt to about 0.5 volt is applied on the source region on the one flash memory device, while maintaining a ground potential on the P-type substrate to inject electrons onto a floating gate to program the floating gate. The source voltage is applied by the bias-potential generation circuit coupled to the source region. The bias-potential generation circuit couples to the source region through the source-bias line.
Numerous benefits are achieved by way of the present method of operating the flash memory cells, and may include one or more of the following advantages. In one implementation, the present invention improves programming efficiency. The present invention is easy to achieve and can be implemented on a variety of physical structures such as stacked gate, split gate, and other structures. The present invention lowers of the threshold voltage of the flash memory cell. The present invention increases programming speed. The present invention achieves one or more of these benefits in one or more embodiments. These and other benefits, however, will be discussed in more detail below.
The present invention achieves these benefits in the context of known proces s technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
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Lee William W. Y.
Lin Shi-Tron
Elms Richard
Nguyen Van-Thu
Townsend and Townsend / and Crew LLP
Winbond Electronics Corporation
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