Receiver with a clock signal generator

Details Receiver with a clock signal generator Receiver with a clock signal generator

1999-11-12

2002-09-10

Pham, Chi (Department: 2631)

Pulse or digital communications

Receivers

C375S323000, C375S334000

Reexamination Certificate

active

06449319

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a receiver comprising a reference frequency oscillator for generating a reference frequency signal having a reference frequency, and a clock circuit for deriving a clock signal from the reference frequency signal.
BACKGROUND OF THE INVENTION
GB-A-2 310 966 describes a communication device which includes circuitry operating at a rate set by a system clock signal. The communication device communicates on any one of a plurality of different channels. A clock circuit outputs the system clock signal at a first frequency which generates spurious signals on at least one of a plurality of different channels. The controller shifts the system clock signal by a first pre-determined amount to a second frequency when the communication device is to be tuned to at least one of the plurality of channels so as to remove spurious signals from the at least one of the plurality of channels.
SUMMARY OF THE INVENTION
It is an object of the invention to allow cost-efficient implementations of a receiver as defined in the opening paragraph.
Let it be assumed that the receiver comprises a frequency converter for converting an input signal in frequency with a conversion frequency so as to obtain an intermediate frequency signal, the conversion frequency being P times the reference frequency divided by M, P and M being integers, P being adjustable.
The invention takes the following aspects into consideration. In many receivers, the intermediate frequency signal must be precise enough in frequency to obtain a satisfactory reception quality. The frequency precision of the intermediate frequency signal depends on the frequency precision of the input signal and on the precision of the conversion frequency. The frequency precision of the input signal is generally relatively good and, consequently, the frequency precision of the intermediate frequency signal IF depends substantially on the conversion frequency precision.
Conversion frequencies which are precise enough may be obtained if the reference frequency is fixed and precise. An adjustment of P by one unit involves a change of the conversion frequency which is equal to the reference frequency divided by M. By changing P unit by unit, a grid of conversion frequencies is thus obtained in which the distance between two adjacent conversion frequencies is the reference frequency divided by M. With such a grid, a relatively satisfactory frequency precision can be obtained at the level of the intermediate frequency so that a satisfactory reception quality is obtained.
In the background art, a synthesizer circuit is used for deriving the clock signal from the reference frequency signal. Accordingly, it is possible to shift the clock signal in frequency while the reference frequency remains fixed. By shifting the clock signal in frequency, it can be prevented that the clock signal causes interference in a channel to which the receiver needs to be tuned.
In accordance with the invention, the receiver comprises a frequency shift circuit for shifting the reference frequency with a frequency shift which is substantially equal to K times the reference frequency divided by a typical value of P, K being an integer. Accordingly, by shifting the reference frequency with the aforementioned frequency shift, it can be prevented that the clock signal causes interference in a desired channel, without substantially affecting the conversion frequency precision. The conversion frequency remains substantially at the grid of conversion frequencies which would be obtained if the reference frequency were not shifted. Since the conversion frequency remains substantially at this grid, the frequency precision at the level of the intermediate frequency is not too much influenced by the fact that the reference oscillator is shifted in frequency. Consequently, the invention allows a satisfactory reception quality without this requiring a synthesizer circuit for deriving the clock signal from the reference frequency signal. Thus, the invention allows cost-efficient implementations.
These and other aspects of the invention are apparent from and will be elucidated, by way of non-limitative example, with reference to the embodiments described hereinafter.


REFERENCES:
patent: 5584068 (1996-12-01), Mohindra
patent: 5612977 (1997-03-01), Ogoro
patent: 5768697 (1998-06-01), Shirakawa
patent: 5825813 (1998-10-01), Na
patent: 5874913 (1999-02-01), Blanchard et al.
patent: 6163229 (2000-12-01), Caspers et al.
patent: 2310966 (1997-10-01), None

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