Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-07-03
2002-01-08
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S762000, C257S773000
Reexamination Certificate
active
06337516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor wiring and more particularly to methods to increase wiring density and to decrease wiring pitch and width within a semiconductor device.
2. Description of the Related Art
Conventional systems form wiring in a semiconductor device by many methods, such a photolithography/etching processes. More specifically, a common method for forming wiring includes depositing a light sensitive photoresist sacrificial mask film, on a substrate and patterning the mask material by exposing it to a light pattern. The light pattern which is exposed on the sacrificial film represents a positive or negative image of the desired wiring pattern. The exposed regions change composition, such that the unexposed areas of the mask have a different etching sensitivity than the exposed regions of the mask.
Once the mask material has been exposed to the wiring pattern of light, a etching process, such as reactive ion etching or chemical etching is performed to remove the exposed regions of a positive photoresist mask or to remove the unexposed regions of a negative photoresist mask. After the etching process, the mask represents a negative image of the desired wiring pattern. This etching process may also be extended to form wiring grooves in the substrate which match the desired wiring pattern.
If grooves are formed in the substrate, the mask is removed from the substrate in a stripping process leaving the bare substrate with a line-space array of wiring grooves. The wiring grooves are then filled with a conductive material, such as copper, and the structure is planarized such that the conductive material remains only within the wiring grooves and the substrate insulates the conductive wiring.
Alternatively, the pattern may be formed on a conductive material which is etched. The remainder of the mask is removed to leave a wiring pattern. Subsequently, an insulator is formed adjacent the wiring pattern to insulate the wiring.
This generally completes the formation of the wiring pattern. Additional wiring levels may be formed by repeating the steps described above. After wiring processes are completed, subsequent processing is then performed to complete the semiconductor device.
However, conventional methods of forming semiconductor wiring are limited by the resolution of the photolithography process. More specifically, the smallest light image which can be focused on the sacrificial mask represents the smallest size wire which can be produced. Similarly, the resolution of the photolithographic process limits the wiring pitch and density which can be formed in semiconductor devices.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for reducing the size of the wires and increasing the wiring density within a semiconductor device. The invention achieves these goals by using a sacrificial (insulating) layer to effectively double the number of copper lines within a layer of wiring. The invention also exploits the process control for certain deposited films and controls the thickness and conformality of the deposit films better than conventional lithography.
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Jones Harris C.
Ryan James G.
McGinn & Gibb PLLC
Neff, Esq. Daryl K.
Quach T. N.
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