Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-04-24

2002-04-30

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S176000, C327S165000, C327S035000

Reexamination Certificate

active

06380778

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a technology of reproducing duty for clock signals so as to lapse into desirable duty by a logic circuit unit operated in synchronism with the clock signals, and to a technology effective for application to a semiconductor integrated circuit.
In a logic circuit comprising a sequence circuit and a combinational circuit, the sequence circuit is normally synchronized with a clock signal to allow a latch operation. In many applications for the logic circuit, the clock signal may preferably be set to a duty ratio of 50% (ratio of high level period to high level and low level periods). In a high-speed operation logic IC, for example, PLL or an oscillator circuit such as a frequency programmable circuit is provided thereinside and each clock is supplied therefrom. Using a differential type circuit as an oscillator circuit such as VCO/ICO or the like makes it possible to generate complementary clock signals whose phase difference/duty ratio are both 50%. However, a duty shift or deviation caused by the difference between a rising propagation delay time tpLH of each clock signal and a falling propagation delay time tpHL thereof is developed in combinational logic provided at a subsequent stage of the oscillator circuit, such as a logic level converter, a clock selection circuit lying inside a logic unit.
The duty shift exerts an influence on the operating speed of the logic circuit. Namely, firstly, the limit of speed-up of a high-speed operation logic circuit is generally determined according to the sum of a delay time for a path (so-called critical path) in which a value obtained by adding (add-subtract calculation) a delay time developed from a clock signal input terminal of a flip-flop to data input terminals of subsequent-stage combinational logic and a next-stage flip-flop via the output of data of the flip-flop, the time required to set up the input of data of the flip-flop on the next-stage side, and a clock skew reaches a maximum within the logic circuit, etc. This value corresponds to a minimum value (maximum value as an operating frequency) determined with respect to the cycle of a clock pulse.
Secondly in addition to the above, operable minimum values are respectively included in an “H” (high level)” width and an “L” (low level) width of a clock input waveform of each flip-flop. When a duty ratio for clocks is shifted from 50%, a high-speed operation limit might be determined in advance in terms of a clock width. This value corresponds to a minimum value determined with respect to each of the “H” and “L” widths other than the cycle of the clock pulse.
The duty ratio for the clock signals is determined according to both the configuration of a clock generator and a shift between tpLH and tpHL in a logic circuit provided at a stage subsequent to the clock generator.
After the invention of the present application has been completed by the present inventors, the present inventors have recognized the presence of first through third Laid-Open Publications. Japanese Patent Application Laid-Open No. Hei 7(1995)-30380 corresponding to the first Laid-Open Publication describes a latch technology of avoiding mistransmission of data between a master latch and a slave latch controlled by quarter-phase clock signals. Japanese Patent Application Laid-Open No. Hei 8(1996)-88545 corresponding to the second Laid-Open Publication describes a technology of transmitting pulse signals inputted to a buffer to a subsequent stage without disturbing a duty ratio. In the present disclosure, a duty ratio correction circuit comprises a series-connected circuit comprised of an edge detection circuit and a latch circuit. Japanese Patent Application Laid-Open No. Hei 7(1995)-21222 corresponding to the third Laid-Open Publication describes a voltage-controlled oscillator which forms an output having a duty ratio of 50%.
In third Laid-Open Publication in particular, differential frequency signals obtained by charging and discharging capacitive elements connected to differential analog input terminals are compared with each other and complementary analog signals are formed from the result of comparison. A latch circuit in which a pair of NAND gates is cross-connected, is used in serial two stages to thereby waveform-shape the complementary analog signals. A delay corresponding to a one-stage gate is developed between the waveform-shaped complementary clock signals. The waveform-shaped complementary clock signals are inputted to a two-input NAND gate. A clock having a narrow width equivalent to the gate delay developed between the input complementary clock signals is formed at the output of the two-input NAND gate. It is divided into two to thereby form clock signals having a duty ratio of 50%. The complementary outputs from the final stages of the serial two-stage latch circuits are fed back to complementarily activate switch circuits for charging and discharging the capacitive elements. In this configuration, the NAND-gate based latch circuits placed in the serial two stages aim to receive an analog output of a comparator and waveform-shape the analog output. Further, the waveform-shaped complementary outputs are fed back as complementary switch control signals for current switch circuits for charging and discharging the capacitive elements placed on the input side of the comparator. Therefore, the serial two-stage NAND latch circuits cannot be formed as components capable of being separated and grasped from the feedback system.
SUMMARY OF THE INVENTION
It is desirable that a duty ratio for clocks is close to 50% to take a high-speed operation margin or increase the maximum operating frequency. It is also desirable that when a duty ratio of 50% takes place at a given node, the difference between tpLH and tpHL is nonexistent at its subsequent stage where practicable. In other words, it has been revealed by the present inventors that it is desirable that the duty ratio of 50% can be achieved at a subsequent stage, i.e., at a clock input terminal of each flip-flop where practicable.
It is considered that in order to achieve the duty ratio of 50% to the utmost, for example, the oscillating frequency is set twice and divided into two by a logic circuit corresponding to a subsequent stage. However, in a high-speed operated application like a read channel LSI such as HDD (Hard Disc Drive), DVD (Digital Video Disc) or the like, the setting of the oscillating frequency to further twice is realistically difficult and undesirable in terms of power consumption and EMI (Electromagnetic Interference).
An object of the present invention is to provide a duty recovery or restoring technology capable of easily recovering a duty ratio for clock signals to a duty ratio of about 50% corresponding to a desirable state in the neighborhood of a sequence circuit even if the duty ratio for the clock signals breaks down at a logic circuit unit which inputs complementary clock signals and performs a logic operation, and a semiconductor integrated circuit to which the technology is applied.
Another object of the present invention is to provide a duty recovery technology capable of easily recovering a duty ratio for clock signals to a state of a desirable about 50% even if the duty ratio for the clock signals increases or decreases from about 50%, and a semiconductor integrated circuit to which the technology is applied.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] According to a first aspect of the present invention, serial two-stage static latches are used to correct duty. Namely, a semiconductor integrated circuit has an oscillator circuit (
2
) which generates complementary cycle signals having a phase difference of about half cycle therebetween and having a duty ratio of about 50%, an output converter (
3
) which con

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