Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-09-11
2002-01-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230040
Reexamination Certificate
active
06335874
ABSTRACT:
FIELD OF INVENTION
The present invention relates to memory array architectures generally and to symmetric memory array architectures in particular.
BACKGROUND OF THE INVENTION
Memory arrays are well known in the art and comprise matrices of memory cells organized into rows and columns. Each memory cell comprises a source, a drain and a gate, each of which has to receive voltage in order for the cell to be accessed. Columns of sources and columns of drains are connected together by bit lines while rows of gates are connected together by word lines. To activate a cell, one drain bit line, one source bit line and one word line must receive voltage.
A standard memory array architecture consists of one metal line on each column, periodically connected to the underlying bit line via a contact. The contact typically is large and is present within the memory array area. The word line is typically of lower resistance and its contact is located outside of the memory array area. There is typically a common source line for a plurality of memory cells. Furthermore, the metal lines are themselves quite thick. Typically, the distance between bit lines is defined by the width of either or both of the metal lines and the contacts, where the contacts are typically wider than the metal lines.
Various memory array architectures are known which reduce the size of the memory array area by reducing the number of contacts and/or metal lines. In virtual ground architectures, the common ground line is eliminated. Instead, the drain of one cell serves as the source for its neighboring cell. Bit lines are continuous diffusions with a contact to the metal lines every X (8, 16, 24, 32, 64, 128, etc.) cells to reduce resistance. The gain in area is up to 40% due to the reduced number of contacts and the elimination of the common source line.
To further reduce array size, the alternate metal, virtual ground architecture (AMG), described in U.S. Pat. No. 5,204,835, has two bit lines per metal line. Typically, in the AMG architecture, the cell size is close or equal to the minimum feature size possible for the cells.
Standard virtual ground architectures access every cell symmetrically (i.e. every bit line receives voltage directly from a metal line). The AMG architecture, which is more compact than standard virtual ground architectures, directly provides voltage to the metalized bit lines but indirectly provides voltage to the segmented, non-metalized bit lines. As a result, the voltage on an activated non-metalized bit line (which is provided through n-channel select transistors) is lower than the voltage on a simultaneously activated metalized bit line. Furthermore, n-channel transistors are not good at passing the high voltages needed for programming.
The non-symmetry of the AMG architecture makes it difficult to use with a nitride read only memory (NROM) array which stores two bits in each NROM cell. Such a cell is described in Applicant's copending application Ser. No. 08/905286, filed Aug. 1, 1997 entitled “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping” and assigned to Saifun Semiconductors, the same assignee as for this application, whose disclosure is incorporated herein by reference. The two bits in a cell are located on each side of the cell and each bit is accessed by voltages on the two neighboring bit lines of the cell. Accordingly, the cell requires that its two neighboring bit lines receive equivalent amounts of voltage thereby to read both bits equally (although not simultaneously).
Some architectures segment the bit lines. Each row of segmented bit lines is called a “block” and each block typically includes block select transistors to activate only one block at a time. This is particularly important for FLASH electrically erasable, programmable, read only memory (FLASH E
E
PROM) arrays which pass high voltages along the bit lines during programming and erase operations. During programming, the bit line voltages disturb the unselected cells. To reduce the total time the programming voltage disturbs the cells, the bit lines are segmented into small blocks.
SUMMARY OF THE PRESENT INVENTION
An object of the present invention is to provide a compact, symmetric architecture.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a symmetric memory array which includes a multiplicity of repeating segments formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines, an even select area, and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.
The architecture of the present invention provides two diffusion bit lines for each metal line, which saves space in the array. The array is symmetric and provides a constant resistance for every cell in the array. The latter is achieved by having segmented cell bit lines which receive power through only one select transistor and by having alternating cell bit lines receiving power from alternating select areas. Thus, each cell has one bit line connected to its upper select area and one bit line connected to its lower select area. As a result, the distance current travels from one contact through the active cell to the other contact is the same for every cell in the array.
Moreover, in accordance with a preferred embodiment of the present invention, the memory cells can be any one of the following types of memory cells: read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), FLASH erasable electrically programmable read only memory (FLASH EEPROM), nitride ROM (NROM), dual bit ROM, and dual bit NROM.
There is also provided, in accordance with an alternative embodiment of the present invention, a symmetric memory array including a multiplicity of memory cells, a plurality of even and odd segmented cell bit lines, and generally half as many metal lines as bit lines. Each of the memory cells is formed between neighboring even and odd cell bit lines. Each metal line provides power to either two consecutive even cell bit lines or two consecutive odd cell bit lines.
Finally, there is provided, in accordance with a preferred embodiment of the present invention, a symmetric memory array including a multiplicity of memory cells, at least one contact region and two select cells. Each memory cell comprises a virtual source region, a virtual drain region and a channel region formed therebetween. The contact region is isolated from the memory cells. One select cell is formed between each contact region and the virtual source region of each of the memory cells and the second select cell is formed between the contact region and the virtual drain region of each of the memory cells. Each memory cell receives power to its virtual regions from contact regions located above and below the memory cell.
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patent: 5477499 (199
Eitan Pearl Latzer & Cohen-Zedek
Elms Richard
Nguyen Hien
Saifun Semiconductors Ltd.
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