Substrate fed logic and method of fabrication

Details Substrate fed logic and method of fabrication Substrate fed logic and method of fabrication

1976-12-22

1978-01-03

Wojciechowicz, Edward J.

357 52, 357 89, 357 90, H01L 2702, H01L 2934

Patent

active

040670384

ABSTRACT:
An integrated circuit having a substrate of a first conductivity type, a first layer of opposite conductivity type thereon and a second layer of said first conductivity type inversely graded on said first layer and including a heavily doped region adjacent the surface opposite said first layer. A ring of said opposite conductivity type extends through said second layer and partially into said first layer and a diffused region of said opposite conductivity type is in the surface of said second layer.
The method of fabrication includes epitaxially forming said first layer on said substrate, expitaxially forming said second layer on said first layer having a decreasing impurity concentration from the P-N junction to the surface, forming said ring, nonselectively diffusing to increase the impurity concentration at the area adjacent the surface of said second layer and selectively diffusing to form said diffused surface region.

REFERENCES:
patent: 4007474 (1977-02-01), Yagi et al.
IBM-Tech. Bul. --vol. --, No. 6, Nov. 1970, P. 1740, H. Ghosh.
IBM-Tech. Bul. --vol. 11, No. 10, Mar. 1969, pp. 1342- 1343, Viva et al.

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