Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor
Reexamination Certificate
2000-11-06
2002-04-30
Reichard, Dean A. (Department: 2831)
Electricity: electrical systems and devices
Electrostatic capacitors
Fixed capacitor
C361S311000, C361S321100, C361S306300, C361S305000, C257S306000, C257S308000, C257S295000, C501S134000, C501S135000, C501S139000
Reexamination Certificate
active
06381119
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P11-314998 filed Nov. 5, 1999, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electronic thin-film material, a dielectric capacitor using such electronic thin-film material, and a nonvolatile memory using such dielectric capacitor.
2. Description of the Related Art
Substantially, a ferroelectric memory is a nonvolatile memory which is capable of executing high-speed rewriting operation by way of utilizing high-speed reversal of polarization of a ferroelectric film and its excellent remnant polarization.
FIG. 6
exemplifies one example of a conventional ferroelectric memory comprising a transistor and a capacitor respectively being disposed in the lateral direction.
As is apparent from
FIG. 6
, in the exemplified conventional ferroelectric memory, a field insulating film
102
is selectively disposed on a surface of a p-type silicon substrate
101
for effecting device isolation. A gate insulating film
103
is formed on a surface of an active area in a portion surrounded by the field insulating film
102
. A reference code WL designates a word line. An n
+
-type source area
104
and an n
+
-type drain area
105
are formed inside of the p-type silicon substrate
101
on both-side portions of the word line WL. The word line WL, the source area
104
, and the drain area
105
jointly constitute a transistor Q.
A reference numeral
106
designates an inter-layer insulating film. A Pt (platinum) film
108
having approximately 200 nm of thickness functioning itself as a lower electrode, a ferroelectric film
109
made of Pb (Zr,Ti) O
3
(PZT) or SrBi
2
Ta
2
O
9
(SBT) having approximately 200 nm of thickness for example, and another Pt film
110
having approximately 200 nm of thickness functioning itself as an upper electrode for example, are sequentially laminated on the inter-layer insulating film
106
at an upper portion of the field insulating film
102
via a Ti (titanium) film
107
having about 30 nm of thickness functioning itself as a bonding layer. The above Pt film
108
, the ferroelectric film
109
, and the Pt film
110
jointly constitute a capacitor C. The above-referred transistor Q and the capacitor C constitute a memory cell.
A reference numeral
111
also designates an inter-layer insulating film. A contact hole
112
is formed through the inter-layer insulating film
106
and the other inter-layer insulating film
111
at an upper portion of the source area
104
. Another contact hole
113
is formed through the inter-layer insulating film
111
at an upper portion of the Pt film
110
. The source area
104
of the transistor Q is connected to the Pt film
108
being a lower electrode of the capacitor C via the contact holes
112
and
113
by means of wiring
115
. Wiring
116
is connected to the Pt film
110
being an upper electrode of the capacitor C via a contact hole
114
. A reference numeral
117
designates a passivation film.
In the conventional ferroelectric memory shown in
FIG. 6
, the transistor Q and the capacitor C are disposed in the horizontal direction in parallel with the surface of the silicon substrate
101
. However, in order to improve data-recording density, it is necessary to dispose the transistor Q and the capacitor C in the direction vertical to the surface of the substrate
101
(this is referred to as a stack-type construction). One embodiment for the stack-type construction is exemplified in FIG.
7
. Those components shown in
FIG. 7
via the reference numerals identical to those shown in
FIG. 6
are respectively designated by way of the identical reference numerals.
In
FIG. 7
, the reference codes WL
1
through WL
4
respectively designate word lines, whereas a reference numeral
118
designates an inter-layer insulating film. A contact hole
119
is formed through the interlayer insulating film
118
at an upper portion of a drain area
105
. A bit line BL is connected to the drain area
105
of a transistor Q via the contact hole
119
. A reference numerals
120
and
121
respectively designate inter-layer insulating films. A contact hole
122
is formed through the inter-layer insulating film
121
at an upper portion of a source area
104
. A polycrystal silicon plug
123
is buried in the contact hole
122
. The source area
104
of the transistor Q and a Pt film
108
of a lower electrode of a capacitor C are electrically connected to each other via the polycrystal silicon plug
123
.
Normally, whenever forming a ferroelectric film
109
, in order to realize crystallization of the film components, it is essential that a thermal treatment process is executed in oxidization atmosphere containing 550° through 800° C. of very high temperature. Nevertheless, during the thermal treatment process, silicon component of the polycrystal silicon plug
123
is thermally diffused into the Pt-film
108
of the lower electrode of the capacitor C to cause the diffused silicon component to be oxidized at the upper layer of the Pt-film
108
, whereby causing the Pt-film
108
to lose own electrical conductivity, and yet, because of further diffusion of the silicon component into the ferroelectric film
109
, the capacitor C incurs significant degradation of own physical characteristics, thus raising a problem.
There is such a technical report suggesting that, when the ferroelectric film
109
is made from PZT (lead-zirconatetitanate) compound material, the PZT is processed via an annealing process at 550° through 600° C. of temperature, whereby enabling to utilize an nitride film such as TiN for composing a barrier layer to prevent silicon component from diffusing into the ferroelectric film
109
. This report was publicized via the lecture of the Applied Physics Academy of Japan held in autumn, 1996, via 7p-F-10, under the title of “Evaluation of oxidation-proof characteristics of a barrier layer comprising a TiN film used for ferroelectric capacitor”.
Nevertheless, the nitride film is oxidized via the thermal treatment process executed at a very high temperature in the oxidization atmosphere, thus losing own electrical conductivity. Thus, in order to further improve ferroelectric characteristics of the ferroelectric film
109
, when sufficient volume of oxygen is fed into the thermal treatment atmosphere to execute the thermal treatment process at a still higher temperature, the oxidization effect causes the film surface to be roughened and electrical resistance to be intensified. Normally, a ferroelectric film generates substantial film stress. However, the nitride film proves to be insufficient in the film adhesion property to cause the film itself to be stripped off, thus raising a problem.
As in the case of such a conventional ferroelectric memory shown in
FIG. 7
, when disposing the transistor Q and the capacitor C in the vertical direction and connecting the Pt film
108
of the lower electrode of the capacitor C to the source area
104
of the transistor Q via the polycrytal silicon plug
123
or a tungsten (W) plug, it is quite difficult to utilize the PZT requiring a high temperature thermal treatment for the material to make up the ferroelectric film
109
of the capacitor C.
SUMMARY OF THE INVENTION
Accordingly, a primary object of the present invention is to provide a novel stack-type capacitor capable of realizing high integration with a simple composition. More particularly, the invention provides a novel electronic ferroelectric film material suitable for composing a barrier layer for preventing silicon component or tungsten component of a plug from diffusing into a lower electrode of a ferroelectric film in the course of connecting the lower electrode of the ferroelectric film to diffusive layer of a transistor via the plug made from polycrystal silicon or tungsten after disposing the transistor and a novel ferroelectric capacitor in the vertical direction, where the novel electronic
Ha Nguyen
Reichard Dean A.
Sonnenchein Nath & Rosenthal
Sony Corporation
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