Single reference plane plastic ball grid array package

Details Single reference plane plastic ball grid array package Single reference plane plastic ball grid array package

2000-08-03

2002-05-28

Wille, Douglas (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S702000, C257S738000, C257S774000, C257S782000, C361S760000, C361S762000, C361S764000

Reexamination Certificate

active

06396140

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the packaging of semiconductor devices, and in particular to a ball grid array (BGA) package.
2. Description of the Related Art
BGA packages for semiconductor devices are becoming increasingly common. A cross-section of one conventional plastic BGA (PBGA) package is illustrated in FIG.
1
. As shown, the package comprises a semiconductor device
10
mounted on a substrate
12
and electrically connected to traces (not shown) on the substrate
12
through bonding wires
14
. Solder balls
16
serve to mount the package to a printed circuit board. The traces are connected to the solder balls
16
through vias
17
in the substrate. The substrate
12
comprises three material layers
20
,
22
and
24
, which comprise pre-preg, a core which is typically BT resin and pre-preg, respectively; the pre-preg thickness is approximately 00.100 mm while the core thickness is approximately 0.500 mm.
The three material layers
20
,
22
and
24
define four metal layers,
26
,
28
,
30
and
32
. Layer
26
comprises a plurality of traces for signal input/output (I/O) and layer
28
20
comprises a metal plane which serves as a reference (ground) to the traces on layer
26
. The traces on layer
26
may also be routed underneath the die. All of the traces on layer
26
, whether or not routed underneath the die, are connected by vias to layer
32
, where signal traces connect vias to the desired solder balls. Layer
30
comprises a partial ground plane and a partial power plane wherein the partial ground plane serves as a reference to the traces on layer
32
. (The partial ground plane is generally directly above the traces for which it is serving as a reference while the power plane may be, for example, a ring that surrounds the ground plane and is not directly above any of those traces.)
It is desirable to improve upon various characteristics package illustrated in FIG.
1
. In particular, traces on the layer
32
must be grouped together and can only be routed in areas where it is possible to provide a reference plane above on layer
30
; these restrictions decrease the available amount of routing space.
SUMMARY OF THE INVENTION
These and other needs are met by the present invention, which comprises a package with multiple routing layers. In particular, according to one embodiment, the present invention comprises a substrate having a top surface with traces thereon and a bottom surface with solder balls thereon, the substrate comprising at least three material layers defining at least four substantially planar metal layers, wherein one of the metal layers comprises a reference layer that serves as a reference to both traces on a routing metal layer above the reference layer and traces on a routing metal layer below the reference layer. A semiconductor die is mounted to the substrate and bonding wires electrically connect the semiconductor die to the traces on the top surface of the substrate. The traces on the top surface of the substrate are electrically connected to the solder balls through vias and possibly through routing on another metal layer.
Since a single layer serves as a reference to two trace routing layers, an additional reference layer is not necessary, which frees up routing space.


REFERENCES:
patent: 4965594 (1990-10-01), Komuro
patent: 5036163 (1991-07-01), Spielberger et al.
patent: 5303119 (1994-04-01), Hilbrink
patent: 5468999 (1995-11-01), Lin et al.
patent: 5500555 (1996-03-01), Ley
patent: 5808873 (1998-09-01), Celaya et al.
patent: 6064113 (2000-05-01), Kirkman
patent: 6127728 (2000-10-01), Juneja et al.
patent: 375461 (1990-06-01), None
patent: 4-61149 (1992-02-01), None
patent: 7-226456 (1995-08-01), None

Affiliated with

Also associated with

Rating

Single reference plane plastic ball grid array package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single reference plane plastic ball grid array package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single reference plane plastic ball grid array package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2842916