Frame aligner including two buffers

Details Frame aligner including two buffers Frame aligner including two buffers

1998-07-01

2002-04-09

Rao, Laura S. (Department: 2732)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S415000, C370S429000, C370S375000, C370S516000, C341S100000, C341S101000

Reexamination Certificate

active

06370162

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frame aligner used in a communication apparatus using an integrated services digital network (ISDN) line when the 8 kHz frame phase of the ISDN line and the 8 kHz frame phase have an arbitrary or uncontrolled phase relationship.
2. Description of the Related Art
Prior art frame aligners include those practically used in transmission apparatuses forming digital transmission paths including those of the primary group (1.544Mb/s) as well as other high speed transmission paths. A prior art frame aligner used in such apparatuses is disclosed in JP-A-6-188871. Also, a prior art frame aligner that is used in apparatuses adapted to transmission paths with a transmission speed lower than that of primary group transmission paths is disclosed in JP-A-3-192839. Any of the prior art frame aligners includes an elastic memory (ES) for the purpose of realizing a data buffering function. An ES used in such a frame aligner is a sort of memory circuit. For example, the ES is constructed by a memory adapted to store data corresponding to 2 frames, a write circuit and a read circuit (see JP-A-6-188871). Also, the ES is constructed by a memory capacity corresponding to a frame of a high speed transmission path (see JP-A-192839).
The above-mentioned prior art frame aligners require an ES having a memory capacity corresponding to a frame or two frames of a high speed transmission path. This capacity will be 193 bits or twice 193 bits in the case of a primary group transmission path, which is very large relative to the 8 bits of the 8 kHz frame of ISDN. In the case where the transmission path is a 2M highway (2. 048Mb/s), a frame corresponds to 256 bits and hence the capacity will be 256 bits or 512 bits. Thus, in this case again, an ES having a very large memory capacity relative to the required capacity will have to be used. Therefore, when one of the prior art frame aligners is applied to an apparatus to be used with a transmission path that is an ISDN, the entire circuit will become very large.
Additionally, when a small capacity frame aligner circuit is used for an apparatus to be used with an ISDN, it will typically be realized in the form of large scale integrated circuit (LSI) along with other component circuits of the apparatus for the purpose of down-sizing and cost reduction. However, the ES of any of the prior art frame aligners normally operates as an independent unit and hence is not adapted to LSI and it is difficult for it to be integrally formed with other circuits. Thus, the prior art frame aligners are accompanied by a problem of the difficulty with which it is down-sized if it is used with an ISDN.
SUMMARY OF THE INVENTION
Therefore, It is an object of the present invention to provide a small size frame aligner adapted to a communication apparatus that uses an ISDN line and having a short frame length.
According to the present invention, in a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit for operating the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal.
Thus, the buffers are provided instead of the ES of the prior art frame aligner, which makes the frame aligner small in size.


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