Reducing contamination induced scumming, for semiconductor...

Details Reducing contamination induced scumming, for semiconductor... Reducing contamination induced scumming, for semiconductor...

1998-09-21

2002-04-16

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C430S291000, C430S313000

Reexamination Certificate

active

06372658

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed generally to a semiconductor method of manufacture. More particularly, the invention relates to such a method involving the reduction or elimination of the adverse effects of contaminants, such as amine airborne-contaminants, which adversely affect types of resists used for photolithography masking.
BACKGROUND OF THE INVENTION
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of a silicon wafer. Integrated circuits of this type are manufactured through a series of steps carried out in a particular order. The main objective in manufacturing such devices is to obtain a device which conforms to geographical features of a particular design for the device. To obtain this objective, steps in the manufacturing process are closely controlled to insure that rigid requirements, for example, exacting tolerances, quality materials, and clean environment, are realized.
Semiconductor devices are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) to form a larger number of devices on a given surface area, the structure of the devices and fabrication techniques used to make such devices must be refined to remove contaminants and structural imperfections.
A wide variety of processing techniques may be employed in manufacturing silicon integrated circuit devices. In those devices, silicon is employed as a semiconductor for conduction of electricity. The chip manufacturing process typically begins with a silicon wafer workpiece. The silicon wafer workpiece is formed of single-crystal silicon (Si). Single-crystal silicon is required because optimization of the final product device depends upon the conformance of the device through each fabrication step to particular geographical arrangements.
Typical steps in the manufacturing process of a silicon integrated circuit device begin with transferring a desired pattern to the surface of a silicon wafer. This pattern may be formed on the wafer surface in a variety of manners. Various materials are formed on the wafer surface in uniform layers or in particular patterns, as desired. A variety of techniques, including, for example, photolithography, may be employed to achieve desired wafer surface configurations.
In photolithography, a photoresist material, for example, a photo-sensitive polymer, may be layered over a somewhat uniform silicon dioxide layer on a wafer surface. A mask having a desired design of clear and opaque areas may then be positioned atop the photoresist layer. Photoresist will selectively respond to UV light. As a result of this selective response characteristic of photoresist, the photoresist can be selectively subjected to UV light and then developed to leave behind an image that will serve as a mask for forming particular patterns of photoresist material atop the silicon dioxide. Once a particular pattern of photoresist is formed atop the silicon dioxide of a wafer, portions of the wafer topped by silicon dioxide but not topped by photoresist may then be etched away from the wafer surface.
Etching is a common procedure employed in manufacture of silicon integrated circuit devices. In general terms, etching is a process by which portions of a workpiece may be selectively removed from the workpiece. The etch process yields a layer on the wafer surface having a desired geographical arrangement, for further processing. After the etch, the photoresist is removed by a subsequent processing step, leaving the silicon wafer topped only by select configurations of silicon dioxide.
The silicon dioxide/photoresist/etch method, generally described above, is extremely involved and requires careful processing steps to ensure accurate device patterning and proper device performance. One of the more important processing steps for the manufacture of silicon wafers may involve exposing the photoresist using deep ultra-violet (DUV) light (about 248 nm range). Photoresists responsive to this level of exposure are referred to as DUV resists.
Many commercially-available DUV resists rely on chemically-amplified resist chemistry. In this approach, DUV exposure causes a component known as a photoacid generator (PAG) to decompose to an acidic species. For positive DUV resists, post-exposure baking (PEB) catalyzes the acid to react to the surrounding polymer which converts the surrounding polymer from base insoluble to soluble. One potential problem with positive chemically-amplified DUV resists is that amines in the surrounding air can be absorbed onto the surface of the resist and neutralize the acid at the surface. When this occurs, the resist at the surface remains insoluble to base even though the underlying resist is soluble. For effective post-PEB development, the entire resist in the exposed areas should be soluble.
The progression leading to this contamination is illustrated in
FIGS. 1
a
through
1
d.
In
FIGS. 1
a
and
1
b,
the illustrated structure is shown after having been exposed to DUV light. The DUV exposure causes unmasked portions
30
of the photoresist to decompose to the acidic species NHR
2
. As shown in
FIGS. 1
c
and
1
d,
the subsequent baking of the exposed resist converts the surrounding polymer from base insoluble to soluble. The absorption of amines onto the surface of the resist is shown as the bridging layer
20
, shown in the form of “T-topping” in
FIG. 1
d.
The desired situation in which the photoresist results in no contamination, is shown
FIG. 1
e.
The typical chemically-amplified resist process overcomes this contamination problem through the use of additional equipment and steps to filter the environment before and while processing the wafers. While this approach is adequate for many applications, there have been pressures to reduce both manufacturing steps and costs, such as the steps and costs associated with environment filtering. In other more-sensitive applications, there is a need to further reduce levels of contamination, for example, by taking steps in addition to conventional environment filtering.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a semiconductor device manufactured using an ashing process in connection with use of a photoresist to eliminate the adverse effects of contaminants such as amine airborne contamination.
Consistent with the present invention, a semiconductor device is formed as part of a wafer. A photoresist is formed over the wafer. The resist-treated wafer is exposed and then baked. Subsequently, the wafer is plasma-treated with an ash to remove the surface layer contaminants, such as amine-contaminants. After ashing, the wafer is developed using conventional processing.
A more particular implementation, consistent with the above-characterized implementation, employs a DUV-type photoresist that is exposed to DUV light, and the ash is applied using a downstream microwave ashing technique.
Other aspects of the present invention are directed to a semiconductor device and a method of manufacturing, each using an ashing method relating to the above process.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.


REFERENCES:
patent: 5201960 (1993-04-01), Starov
patent: 5429910 (1995-07-01), Hanawa
patent: 5792590 (1998-08-01), Hirasawa
patent: 5968374 (1999-10-01), Bullock
patent: 6096484 (2000-08-01), Azuma
patent: 6309804 (2001-10-01), Ziger
Wolf et al. “Silicon Processing for the VLSI Era” vol. 1, Lattice Press, 1986, p. 427-429.*
VLSI.204PA entilted “Reducing Contamination Induced Scumming, for

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