Method to prevent copper CMP dishing

Details Method to prevent copper CMP dishing Method to prevent copper CMP dishing

1999-08-23

2002-05-21

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S751000, C438S754000, C438S756000, C438S697000, C438S687000, C216S088000, C216S105000

Reexamination Certificate

active

06391780

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to formation of copper based damascene wiring.
BACKGROUND OF THE INVENTION
A number of problems faced the semiconductor industry as wiring grew ever smaller and more complex. As the number of layers associated with the completed structure grew so did the problem of planarization become more acute. Additionally, as inter-metal dielectric layers grew thinner, possible leakage problems due to incomplete coverage of wiring by the deposited dielectric material became more likely. Still another problem was that metals having better conductivity than aluminum (such as copper or silver) were needed to improve the conductance of the thinner wires. These metals are known to be rapid diffusers that ‘poison’ silicon so they needed to be confined by diffusion barriers. Similar problems to the already mentioned dielectric coverage problems then arose in connection with such barrier layers.
A solution to many of the above problems has been to use damascene wiring. The term ‘damascene’ is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, instead of forming wiring on a planar dielectric surface, trenches are first etched in the dielectric and then filled with the conducting metal.
In practice, filling of the trenches in damascene wiring is accomplished by first overfilling and then planarizing the resulting surface until all metal outside the trench has been removed. Ideally, the metal and dielectric surfaces will be exactly coplanar in the final product. Conventional etching is unsuitable for planarizing as the etch front tends to follow the contours of the initial surface and/or selectively etch some parts relative to others. Mechanical polishing, long used in the optical industry, was known to remove material along a planar front but was associated with surface damage that could not be tolerated in semiconductor structures.
To overcome the problems associated with purely mechanical polishing, the process called chemical mechanical polishing (CMP) was developed. As the name implies, surfaces subjected to CMP are exposed to both chemical and mechanical polishing simultaneously. What CMP provided was the ability to remove material along an approximately planar etch front at reasonable rates without leaving behind a damaged surface. This made CMP highly attractive as a means for planarizing a surface and it has been used for this purpose by the semiconductor industry for some years.
The removal rate of material from a surface undergoing CMP, is controlled by a number of factors including the hardness and size of the slurry particles, the reactivity of the slurry liquid, the flow rate at which slurry is introduced, the rotational speed of the platen, and the force (pressure) between the surface being polished and the platen.
Although CMP has enjoyed great success as a planarization technique, it is not without its problems. A particular example of this is when a surface comprising a mix of hard and soft materials needs to be planarized as is the case when damascene wiring is being manufactured.
Referring now to
FIG. 1
, we show a schematic cross-section of a dielectric layer
11
(the top-most layer of an integrated circuit wafer at some stage in the manufacturing process) in whose upper surface several trenches, such as
13
a
and
13
b
, have previously been formed. Copper layer
12
has been deposited over
11
in a sufficient quantity to ensure that all the trenches have been over-filled with the copper. This gives the copper layer
12
an upper surface that consists of peaks, such as
14
, and valleys, such as
15
. CMP is now to be used to remove all copper that is not in the trenches, i.e. leaving the trenches just-filled while at the same time removing all traces of copper from everywhere else on layer
11
's upper surface.
A typical result obtained using CMP technology of the prior art is illustrated in FIG.
2
. At the process point where the surface of
11
appears to be free of copper, it is found that considerable dishing
25
of the trenches has occurred so that, instead of being just-filled, the trenches are under-filled. This is a consequence of the fact that, as the surface of
11
was being approached, the polish rate above the hard dielectric became significantly slower relative to the polish rates over areas where copper extended for a significant depth.
In practice it is often necessary to continue CMP beyond the stage illustrated in
FIG. 2
because of residual copper traces still present on surfaces away from the trenches, causing the dishing to become even more severe than illustrated in FIG.
2
.
The present invention teaches how damascene wiring may be formed in which the trenches are just-filled with copper while at the same time removing all traces of copper everywhere else. A routine search of the prior art was conducted but no references teaching the exact method of the present invention were found. Several references of interest were, however, seen. For example, Joshi et al. (U.S. Pat. No. 5,731,245) teach the use of a tungsten-germanium alloy as a hard cap for surface passivation and also as a polish stop. They emphasize that the slurry must have a hardness at least twice that of the metal being subjected to CMP.
Chow et al. (U.S. Pat. No. 4,789,648) give one of the earliest descriptions of the dual damascene process, including overfilling and then planarizing with CMP.
Krishnan et al. (U.S. Pat. No. 5,451,551) use two different barrier layers which enables them to achieve full planarization as well as full barrier protection of the conductor in a single operation.
Schacham-Diamand et al. (U.S. Pat. No. 5,824,599) show how a damascene trench may be filled with copper using an electroless process, following which conventional CMP is used to achieve planarization.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for filling a trench in a hard dielectric material with a layer of soft material whereby at the conclusion of the process no dishing of the soft material within the trenches has occurred.
Another object of the invention has been to provide a process for the formation of damascene wiring in an integrated circuit, particularly with copper as the metal.
A further object of the invention has been that said process be fully compatible with existing processes for manufacturing integrated circuits.
These objects have been achieved by first over-filling the trenches with the soft material (such as copper) and then depositing on the copper surface a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc. Under a first set of control conditions CMP is applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.


REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5451551 (1995-09-01), Krishnan et al.
patent: 5731245 (1998-03-01), Joshi et al.
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 5824599 (1998-10-01), Schacham-Diamond et al.
patent: 6004188 (1999-12-01), Roy
patent: 6017803 (2000-01-01), Wong
patent: 6051496 (2000-04-01), Jang

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