Pulse or digital communications – Spread spectrum
Reexamination Certificate
1999-05-28
2002-09-17
Chin, Stephen (Department: 2734)
Pulse or digital communications
Spread spectrum
C380S268000
Reexamination Certificate
active
06452959
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to the field of communications, as well as to the field of data sequence generators. More particularly, many embodiments of the invention relate to pseudorandom noise (PN) sequence generators for use in Direct Sequence Spread Spectrum (DSSS) communication systems.
II. Description of the Related Art
In direct sequence spread spectrum (DSSS) communication systems, such as Code Division Multiple Access (CDMA) systems, pseudorandom noise (PN) sequences are used to generate spread spectrum signals by increasing the bandwidth (i.e., spreading) of a baseband signal. In conventional methods, PN sequences are generated with PN generators that make use of Linear Feedback Shift Registers (LFSRs). An LFSR has a shift register of N stages and intervening exclusive-OR gates for programming a specific PN sequence. A subset of the PN sequences generated by the N-stage LFSR are characterized as maximal length (ML) PN sequences, and are of length 2
N
−1.
As an example, an ML PN sequence of length seven: (1) may be characterized as having seven states: (2) has associated with it six versions of the Nominal PN Sequence shifted by a non-zero number of PN chips; and (3) has three delay elements are required for operation.
FIG. 1
is a block diagram of a conventional LSFR
100
for generating an ML PN sequence of length seven. LFSR
100
has three delay elements
102
,
104
, and
106
, and adder
108
, a clock signal
110
, and an output
112
providing the PN sequence. Addition is performed modulo two by adder
108
. Clock signal
110
having a frequency equivalent to the rate of change of the state of the PN output sequence generated at output
112
.
Table 1 below sets forth the six shifted versions of a periodic Nominal PN Sequence of length seven produced by LFSR
100
of FIG.
1
. The bit patterns included with each row of the PN Sequence column correspond to the sequential values of the PN output sequence at output
112
(FIG.
1
).
TABLE 1
PN SEQUENCES ASSOCIATED WITH THE LFSR OF
FIG. 1
DELAY IN
NOMINAL PN SEQUENCE
PN SEQUENCE
0
1010011
(NO SHIFT)
(NOMINAL)
1
1101001
2
1110100
3
0111010
4
0011101
5
1001110
6
0100111
Table 2 below provides a representation of the value of a nominal PN output sequence at output
112
as a function of the state of LFSR
100
. The sequence of three bits within each row of the left hand column of Table 2, correspond (from left to right) to the outputs of delay elements
102
,
104
, and
106
(from left to right). The corresponding value of the output bit (i.e., chip) produced by LFSR
100
in response to a given LFSR state is set forth in the right hand column.
TABLE 2
CHIP VALUE PER GIVEN STATE FOR LFSR OF
FIG. 1
LFSR STATE
CHIP VALUE IN PN OUTPUT SEQUENCE
111
1
110
0
011
1
100
0
010
0
001
1
101
1
In the communication systems where these LFSRs are used, it is often necessary to obtain shifted versions of PN sequences as well. Most desirable, shifted PN sequences need to be obtained in a time effective and direct manner (i.e., somewhat immediately). In direct sequence transmitters, for example, PN sequence shifting is required to enable the output of the transmitter's PN sequence generator to be aligned with some particular system time. In direct sequence receivers, PN sequence shifting is necessary to align the output of the receiver's PN sequence generator to the timing of a received waveform so as to enable despreading. In addition, PN sequence shifting is required for purposes of PN timing acquisition and multipath detection.
For any PN sequence of length L, there exists L−1 versions of the sequence which may be defined based on non-zero shifts of the sequence with respect to a reference sequence (“Nominal PN Sequence”). The L−1 shifted versions of the PN sequence of length L may be derived by delaying the Nominal PN Sequence by from one to L−1 PN chips. Circuits similar to the LFSR
100
of
FIG. 1
may be augmented with sequence shifting circuitry to enable generation of an arbitrarily shifted version of a given PN sequence.
A block diagram of a conventional LFSR circuit
200
is shown in
FIG. 2
which provides arbitrarily shifted versions of a PN sequence having a length of seven. This conventional technique is based on the use of a modulo two sum of outputs of particularly selected delay elements of an additional LFSR (although a single LFSR may be used). Such techniques are predicated on the mathematical property that all possible shifted versions of a Nominal PN Sequence may be obtained through the modulo two addition of appropriately selected delay elements.
LFSR circuit
200
includes a primary LFSR
202
, a secondary LFSR
204
, and a masking circuit
206
. As indicated, the state of the primary LFSR
202
is conveyed to secondary LFSR
204
by providing the value of each delay element within the primary LFSR
202
to a corresponding delay element within secondary LFSR
204
. Although the PN sequence produced by secondary LFSR
204
will be identical to the Nominal PN Sequence produced by primary LFSR
202
, the PN sequence produced by mask circuit
206
will be shifted from the Nominal PN Sequence by an offset in the manner described below. By coupling other secondary LFSRs and associated mask circuits to primary LFSR
202
, a set of PN sequences of different offsets relative to the Nominal PN Sequence may be generated.
LFSR circuit
200
includes a set of two adders for performing modulo two addition. The adders are incorporated within the LFSR circuit
200
in such a manner that the Nominal PN sequence, the PN sequence, and the shifted PN sequence are all maximal length. The AND elements function to select outputs of the delay elements in accordance with the selection values M
1
, M
2
, and M
3
provided by a controller (not shown). An active (binary value 1) selection value enables the output of the corresponding delay element to be summed modulo two at the adder with the outputs of other delay elements so selected, and an inactive selection value prevents the sum from occurring.
Table 3 below sets forth the six shifted versions of a periodic Nominal PN Sequence of length seven produced by LFSR circuit
200
of FIG.
2
. The bit patterns included within each row of the PN Sequence column correspond to the sequential values of a particular shifted PN output sequence. As is indicated in Table 3, each PN output sequence is shifted relative to the Nominal PN Sequence by an amount determined by the combination of the selections of M
1
, M
2
and M
3
.
TABLE 3
PN SEQUENCE SHIFTS FOR LFSR CIRCUIT OF
FIG. 2
SEQUENCE CHARACTERISTIC
SELECTION VALUE
SHIFT (DELAY)
M1
M2
M3
RELATIVE TO NOMINAL
PN SEQUENCE
0
0
1
0
1010011
(NOMINAL)
0
1
0
2
1110100
0
1
1
6
0100111
1
0
0
1
1101001
1
0
1
3
0111010
1
1
0
4
0011101
1
1
1
5
1001110
During operation, secondary LFSR circuit
204
is provided with a load signal (not shown) which causes the delay elements to latch the LFSR state registered by the corresponding delay elements of primary LFSR circuit
202
. This causes the PN sequence provided by secondary LFSR
204
upon the output line to become aligned with the Nominal PN Sequence. However, such alignment will be maintained only so long as the clock signals provided to primary LFSR
202
and secondary LFSR
204
do not differ. When such a difference in clock signals arises, the PN sequence produced by secondary LFSR
204
will no longer be aligned with the Nominal PN Sequence.
No relationships are known to exist between the desired shift and the mask needed to generate such shift. Therefore, these masks are stored in a lookup table and accessed when a particular shift is desired. However, much memory space is consumed even if a limited number of masks are stored in connection with a PN sequence having a relatively long length. For example, 15,360 mask bits need to be stored if 512 masks are used in connection with a PN sequence having length 2
15
−1. After using a mask to obtain a “coarse” PN shift, subsequent slewing is required
Brady III W. James
Chin Stephen
Dot Wireless, Inc.
Hernandez Pedro P.
Jiang Lenny
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