Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1997-12-23
2002-03-19
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S692000, C257S693000, C257S696000, C257S728000
Reexamination Certificate
active
06359331
ABSTRACT:
TECHNICAL FIELD
This invention relates to high power switching modules and methods of making same.
BACKGROUND ART
A power switching module may consist of one switch having one or more silicon dies or two switches configured in a half bridge configuration, four switches configured in an H-bridge configuration, or six switches in a three phase bridge configuration, etc. The switches in the module have to be interconnected based on the circuit topology. The interconnections must be carefully designed and laid out to insure that the stray inductance in the bus is kept to a minimum in order to reduce the peak overshoots during turn-off of the switch and during the commutation of the antiparallel diode.
The design approach normally used to reduce the stray inductance is to keep the lead and trace lengths short and to layout the current flow path such that they help in cancelling the fields. Furthermore, the design approach typically involves a single tier design in which the silicon die, device interconnects, and power circuit input and output interconnects are all on the same level on the substrate, as shown in FIG.
1
. This approach works well in a single switch module. It is also possible to extend this approach to a half bridge module and to some extent minimize the stray inductance. However, in a three phase module this approach results in significant stray inductance.
Thus, there exists a need for a circuit layout design for interconnecting the circuit terminations in a power switching module that minimizes stray inductance for various possible switch configurations and is easy to manufacture.
DISCLOSURE OF THE INVENTION
It is thus a general object of the present invention to provide an interconnection scheme for circuit terminations in high power switching modules that minimizes stray inductance.
In carrying out the above object and other objects, features, and advantages of the present invention, a unique power switching module is provided. The module includes a negative rail layer for providing a negative power supply to the power switching module and a positive rail layer for providing a positive power supply to the power switching module wherein the negative and positive rail layers are co-planar with respect to each other. The module also includes a phase output layer for providing a phase output signal from the power switching module. Each of the layers are electrically insulated from each of the other layers. The module further includes a substrate having at least one silicon die forming at least one switching element and corresponding leadframe terminal posts extending away therefrom. Each of the layers are connected to certain terminal posts to provide electrical connection between the substrate and each of the layers.
In further carrying out the above object and other objects, features, and advantages of the present invention, a method is also provided for making the above described power switching module. The method includes the step of providing a substrate having at least one silicon die forming at least one switching element and having corresponding leadframe terminal posts extending therefrom. The method also includes the steps of positioning a negative rail layer providing a negative power supply to the power switching module and a positive rail layer providing a positive power supply to the power switching module on the substrate wherein the negative and positive rail layers are co-planar with respect to each other. The method further includes the step of positioning a phase output layer providing a phase output signal onto the substrate and negative and positive rail layers, wherein each of the layers are connected to certain terminal posts to provide electrical connection between the substrate and each of the layers.
The above object and other objects, features and advantages of the present invention are readily apparent from the following detailed description of the best mode for carrying out the invention when taken in connection with the accompanying drawings.
REFERENCES:
patent: 3349481 (1967-10-01), Karp
patent: 3374400 (1968-03-01), Tabuchi et al.
patent: 4249196 (1981-02-01), Durney et al.
patent: 5103283 (1992-04-01), Hite
patent: 5177670 (1993-01-01), Shinohara et al.
patent: 5200364 (1993-04-01), Loh
patent: 5528073 (1996-06-01), Gilmore
Miller John Michael
Rinehart Lawrence Edward
Sankaran Venkateswara Anand
Loke Steven
Stec Jennifer M.
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