Voltage converter

Details Voltage converter Voltage converter

2001-02-08

2002-09-24

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S272000

Reexamination Certificate

active

06456051

ABSTRACT:

The present invention relates to a voltage converter and in particular but not exclusively to DC—DC converters.
DC—DC converters are used to convert an input unregulated DC voltage to regulated or variable DC voltage at the output.
A known step down DC—DC converter
1
is shown in FIG.
1
. An input voltage Vin is connected to the source of a PMOS transistor
2
. The input voltage is derived from either a rectified alternating current supply or can be supplied directly from a direct current supply. The drain of the PMOS transistor
2
is connected in series to an inductor
8
and to the cathode of a diode
6
. The diode
6
is configured as a fly wheel diode and the anode of that diode
6
is connected to ground. The fly wheel diode
6
supplies a current path for the inductor
8
when the PMOS transistor
2
is switched off.
The converter
1
also has a capacitor
10
which is connected in series to the inductor
8
. The diode
6
is connected to one end of the inductor
8
with the capacitor
10
connected at the other end of the inductor
8
. The capacitor
10
is also connected to ground. The capacitor
10
is in parallel with an output load in the form of a resistor
12
. Again, the resistor
12
is also connected to ground. The capacitor in parallel with the output load acts to suppress output current ripples. pulse width modulator
4
is connected to the gate of the PMOS transistor
2
. The output of the pulse width modulator
4
determines whether the PMOS transistor
2
is on or off.
The output of the circuit is Vo and is provided by node A which is connected to the resistor
12
, the capacitor
10
and the inductor
8
.
The output voltage Vo is controlled by varying the amount of time for which the PMOS transistor
2
is switched on. The amount of time for which the PMOS transistor
2
is switched on is controlled by the pulse width modulating circuit
4
. The pulse width modulator
4
directly controls the switching of the PMOS transistor
2
. The pulse width modulator
4
of
FIG. 1
operates with a fixed frequency and variable duty cycle. This means that by controlling the duty cycle of the output of the pulse width modulator, the amount of power delivered to the load
12
is controlled. An increased switching frequency is disadvantageous in that there are higher switching losses and increased interference.
FIG. 2
shows another known DC—DC converter. This circuit is similar to that shown in FIG.
1
and the same components are referenced by the same numerals. However, a feedback path is provided. This feedback path originates from node A and Vfb is fed back to the pulse width modulator
4
. There is also a reference voltage Vref supplied to the pulse width modulator. The pulse width modulator
4
compares the voltage Vfb fed back from node A with the reference voltage Vref. Based on the comparison of these two voltages, the duty cycle output by the pulse width modulator
4
is determined.
The pulse width modulator
4
is shown in more detail in FIG.
3
. The pulse width modulator
4
has an error signal amplifier
14
which receives the feedback voltage Vfb and the reference voltage Vref. The error amplifier
14
provides an output signal which is the difference between the reference voltage Vref and the feedback voltage Vfb, but amplified.
The output of the error amplifier
14
is connected to the input of a comparator
20
. The comparator
20
also receives the output of a saw tooth generator
18
. The comparator
20
effectively modulates the output of the saw tooth generator
18
with the error signal from the error amplifier
14
. The modulated signal controls the width of the signal applied by the pulse width modulator
4
to the PMOS transistor
2
. The modulated signal is output by the comparator
20
to a output buffer
22
which in turn outputs the signal to the gate of the PMOS transistor
2
. If the output voltage Vo is to be increased, the width of the signals output by the pulse width modulator will be increased and vice versa.
However, one problem with the arrangement shown in
FIG. 2
is that there is no control on the output current under normal and short circuit operation. The behavior of the pulse width modulator
4
is therefore unpredictable. Clearly this is disadvantageous. Relatively large unwanted currents may flow through the converter. This is again undesirable.
It is therefore an aim of embodiments of the present invention to address this problem.
According to one aspect of the present invention there is provided a voltage converter circuit comprising an input; an output; a current control arrangement for controlling the output current of said circuit, said current control arrangement comprising a first mode when the voltage output by said converter circuit is above a threshold voltage and a second mode in which the voltage output by said circuit is below said threshold voltage, said first and second modes being controlled by the same current control arrangement.


REFERENCES:
patent: 3585491 (1971-06-01), Petersen
patent: 4017789 (1977-04-01), Morris
patent: 4128866 (1978-12-01), Doerre
patent: 4791544 (1988-12-01), Gautherin et al.
patent: 4929882 (1990-05-01), Szepsi
patent: 5422562 (1995-06-01), Mammano et al.
patent: 5969515 (1999-10-01), Oglesbee
European Standard Search Report from the British priority Application filed Feb. 15, 2000.

Affiliated with

Also associated with

Rating

Voltage converter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Voltage converter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Voltage converter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2839847