Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-07-19
2002-03-26
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S067000, C345S063000, C315S169100, C315S169200, C313S306000, C313S309000, C313S336000, C313S351000
Reexamination Certificate
active
06362800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a flat panel display device, and more particularly to a method of driving a plasma display panel(PDP) that is capable of improving the brightness of the PDP and an apparatus thereof.
2. Description of the Prior Art
Nowadays, there have been actively developed flat panel display devices such as a liquid crystal display(LCD), a field emission display(FED), a plasma display panel (PDP) and so on. In the flat panel display devices, the PDP has advantages in that its manufacturing is easy due to its simple structure and that it has a high brightness and a high luminous efficiency compared with other flat panel display devices. Also, the PDP provides the improved memory ability and a wide light view angle of more than 160° C. Furthermore, the PDP device has an advantage in that it can implement a large-scale screen of more than 40 inches. Such a PDP is classified into a direct current(DC) system and an alternating current(AC) system. As shown in
FIG. 1
, the PDP of conventional AC system includes a lower glass substrate
10
mounted with address electrodes
12
and an upper glass substrate
20
mounted with a sustaining electrode pair
22
. On the lower glass substrate
10
mounted with the address electrodes
12
, a desired thickness of lower dielectric thick film
14
for generating a wall charge and a barrier rib
16
for dividing discharge cells are sequentially formed. A desired thickness of fluorescent film
18
is coated on the surface of the lower dielectric thick film
14
and the wall surface of the barrier rib
16
. At the bottom side of the upper glass substrate
20
mounted with the sustaining electrode pair
22
, an upper dielectric thick film
24
and a protective film
26
are sequentially formed. The upper dielectric thick film
24
generates a wall charge like the lower dielectric thick film
14
, and the protective film
26
protects the upper dielectric thick film
24
from an impact due to a gas ion during plasma discharge.
The conventional driving principle of the PDP will be described in conjunction with FIG.
2
. As shown in
FIG. 2
, a panel
30
has n first sustaining electrodes Y
1
to Yn and n second sustaining electrodes Z
1
to Zn arranged alternately in parallel to each other m address electrodes Al to Am are arranged perpendicularly to the first and second sustaining electrodes Y
1
to Yn and Z
1
to Zn discharge cells
32
are provided at each intersection between the address electrodes Am and the first and second sustaining electrodes Yn and Zn. The discharge cells
32
are divided by the barrier ribs
16
and a mixture gas of He+Xe or Ne+Xe is sealed into the discharge cells
32
. If a desired voltage is applied between the address electrode
12
and the first sustaining electrode Yn to drive the PDP, then an address discharge is generated to select the discharge cells
32
. At this time, a wall charge is accumulated in the discharge cells
32
by the address discharge to lower a voltage for the sustaining discharge. Subsequently, if a desired voltage is applied between the first and second sustaining electrodes Yn and Zn only at the cells selected by the address discharge, then vacuum ultraviolet rays are generated by the sustaining discharge. At this time, fluorescent materials included in the fluorescent film
18
with red(R), green(G) and blue(B) colors is radiated by the vacuum ultraviolet rays to thereby emit R, G and B visible light rays. The visible rays generated from the fluorescent film
18
are emitted by way of the upper glass substrate
20
to thereby display a picture including characters and graphics.
Generally, a cathode ray tube(CRT) controls an intensity of an electron beam irradiated onto the fluorescent body so as to express the gray scale of a picture. However, since it is difficult the PDP of AC system to control a discharge intensity by such a method, the PDP of AC system expresses the gray scale of a picture by controlling a discharge frequency per hour. In other words, when it is assumed that a time displaying a single image on the entire screen once and sustaining the image be one frame, one frame is divided into n sub-fields. Each cell is turned on only at the corresponding sub-field in each sub-field to generate a discharge, whereas it is turned off at the other sub-fields not to generate a discharge. Accordingly, the brightness of each cell is determined by combining a discharge frequency at the discharged sub-field to thereby implement a gray scale of
2
n
. A typical gray scale implementation method based on the concept as described above includes the addressing and display separation(ADS) system. The ADS system will be described in conjunction with
FIG. 3
below.
FIG. 3
is a view for explaining the conventional PDP driving method. As shown in
FIG. 3
, one frame is divided into 8 sub-fields SF
1
to SF
8
so as to implement 256 gray scales. Each sub-field is divided into a reset interval, an address interval and a sustaining interval and then driven.
The reset interval is a time period for initializing a screen by writing the entire screen simultaneously and thereafter erasing the entire screen. To this end, a writing pulse is applied between the first sustaining electrodes Y
1
to Yn and the second sustaining electrodes Z
1
to Zn simultaneously to turn on all the cells on the screen. Subsequently, an erasing pulse is applied between the first sustaining electrodes Y
1
to Yn and the second sustaining electrodes Z
1
to Zn simultaneously to turn off all the cells on the screen, thereby initializing the entire screen.
The address interval is a time period for selectively discharging only the cells to be turned on at the corresponding sub-field. To this end, −Vs voltage is applied to the first sustaining electrode at a line intended to perform an addressing, whereas Va voltage is applied only to the address electrode at the cell to be turned on in m×3 cells connected to the first sustaining electrodes. At this time, since the sum of Va voltage and Vs voltage is higher than a critical voltage required for a discharge, an address discharge is generated at the cell applied with Va to form a wall charge. Also, since the Vs voltage is lower than the critical voltage, the cell applied with Va does not generate an address discharge. When such a process is sequentially and repeatedly performed n times with respect to n horizontal lines, n×(3m) cells are addressed.
In the sustaining interval, only the cell generating an address discharge performs a sustaining discharge to display and sustain the cell turned on. To this end, a sustaining pulse having Vs voltage is alternately applied between the first and second sustaining electrodes Yl to Yn and Z
1
to Zn in a state in which OV is applied to the address electrodes Al to Am. When one frame is divided into 8 sub-fields, a weighting value of 1:2:4:8: . . . :128 ratio is given in the sustaining interval to express a gray scale by the combination of the sustaining intervals. The sub-field intervals corresponding to each bit are displayed in a sequence of SF
1
, SF
2
, SF
3
, SF
4
, SF
5
, SF
6
, SF
7
and SF
8
.
Meanwhile, since each sub-field SF
1
to SF
8
has different sustaining intervals while having an interval for resting and addressing the entire screen, the reset and addressing intervals becomes same at the
8
sub-field. An efficiency of an ADS system in which a time for one frame is 16.67ms(i.e., {fraction (1/60)} second) will be calculated. Assuming that a time required for a resetting per one sub-field be 200&mgr;s, since one frame is 200&mgr;s ×8 sub-fields, a time of about 1.6ms is required. Also, assuming that a time required for an address interval be 3 &mgr;s, since one frame having 480 horizontal lines is 200 &mgr;s×480 lines ×8 sub-fields, a time of about 11.52 ms is required. In this case, a sustaining interval contributing to the real brightness in the entire frame time of 16.67 ms is 3.55 ms, a low light efficiency of 20.1% is ob
Fleshner & Kim LLP
LG Electronics Inc.
Nguyen Jimmy H.
Shalwala Bipin
LandOfFree
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