Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-31
2002-07-30
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270
Reexamination Certificate
active
06426894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for writing data to a non-volatile semiconductor memory device. More particularly, the present invention relates to a method and a circuit for writing data to a non-volatile semiconductor memory device based on a write operation using secondary electrons.
2. Description of the Related Art
An ETOX (registered trademark of Intel; EPROM Thin Oxide) type non-volatile semiconductor memory device is the most widely used conventional non-volatile semiconductor memory device (a flash memory). Japanese Patent Publication for Opposition No. 6-82841 (Conventional Example 1) discloses a non-volatile semiconductor memory device of this type. Referring to
FIG. 1
, the structure of a cell of an ETOX type non-volatile semiconductor memory device will be described. The non-volatile semiconductor memory device cell includes a source
14
a
and a drain
14
b
which are formed on a substrate
10
, with a channel layer
14
c
extending therebetween. A floating gate
16
is provided over the channel layer
14
c
via a tunnel oxide film
15
. Moreover, a control gate
18
is provided over the floating gate
16
via an interlayer insulating film
17
.
The principle of operation of an ETOX type non-volatile semiconductor memory device will now be described. Table 1 shows voltages to be applied respectively to the control gate
18
, the source
14
a,
the drain
14
b
and the substrate
10
in a write mode, an erase mode, and a read mode.
TABLE 1
Control
gate
Drain
Source
Substrate
Write
10
V
6 V/0 V
0 V
0 V
Erase
−9
V
Open
6 V
0 V
Read
3
V
1 V
0 V
0 V
In the write (programming) mode, a voltage of 10 V, for example, is applied to the control gate
18
of the memory cell to which data is to be written, a reference voltage of 0 V, for example, is applied to the source
14
a
thereof, and a voltage of 6 V, for example, is applied to the drain
14
b.
Then, a current of 500 &mgr;A/cell flows through the channel layer
14
c,
thereby generating channel hot electrons (hereinafter, referred to as “CHEs”) in a portion of the drain
14
b
side of the memory cell where there is a high electric field. Basically, CHEs are high-energy electrons which are generated by a high electric field and which flow through the channel. When CHEs jump over the energy barrier of the tunnel oxide film so as to be injected into the floating gate
16
, the threshold voltage of the memory cell increases. The drain of each memory cell to which no data is to be written is set to the reference voltage (e.g., 0 V). The memory cell to which data has been written as described above has a threshold voltage equal to or greater than 3.5 V as shown in
FIG. 2
by the curve labelled “Programmed state (a)”.
In the erase mode, a voltage of −9 V, for example, is applied to the control gate
18
and a voltage of 6 V, for example, is applied to the source
14
a,
whereby electrons are withdrawn from the floating gate
16
on the source
14
a
side of the memory cell, thereby reducing the threshold voltage. In such a case, the memory cell has a threshold voltage as shown in
FIG. 2
by the curve labelled “Erased state (b)”. Thus, the threshold voltage of the memory cell whose data has been erased is less than or equal to 2.0 V.
For a memory cell to/from which data has been written/erased, a read operation can be performed by applying a voltage of 3 V to the control gate
18
and a voltage of 1 V to the drain
14
b,
while controlling the potential of the source
14
a
to be 0 V. Under such voltage conditions, if data stored in the memory cell is in the programmed state, the threshold voltage of the memory cell is equal to or greater than 3.5 V. Therefore, no current flows through the memory cell, whereby the data in the memory cell is determined to be “0”. If data stored in the memory cell is in the erased state, the threshold voltage of the memory cell is less than or equal to 2.0 V, and a current flows through the memory cell, whereby the data in the memory cell is determined to be “1”.
The write operation will now be described in greater detail with reference to FIG.
3
.
FIG. 3
illustrates the structure of a write circuit of Conventional Example 1.
The write circuit includes a memory cell array
300
including a plurality of memory cells N (M
00
, M
01
, . . . , M
12
) which are arranged in a matrix. Data can be electrically written to or erased from each of the memory cells M. The memory cells M are grouped into one or more blocks. In the example illustrated in
FIG. 3
, one block includes six memory cells. Each of the memory cells M
00
, M
01
, . . . , M
12
in the memory cell array
300
has a field effect transistor including the floating gate
16
and the control gate
18
. The sources
14
a
of the memory cells M in each block are coupled to a common source line
14
A so that they are electrically connected to each other.
The write circuit of
FIG. 3
further includes a row decoder
320
for supplying a voltage signal to the control gate
18
of each of the memory cells M via a word line WL, a program voltage application circuit
340
for applying a voltage signal to the drain
14
b
of the memory cell M via a bit line BL, a source voltage application circuit
360
for applying a voltage signal to the common source line
14
A, and a high voltage charge pump
380
for supplying a voltage to these circuits (
320
,
340
and
360
).
An exemplary write operation will now be described while describing the details of the write circuit of FIG.
3
. Consider a case where data “0” (write enabled) and data “1” (write prohibited) are written to the memory cells M
00
and M
10
, respectively, which are connected to the word line WL
0
, while no data is written to the memory cells M
01
, M
11
and M
02
, M
12
, which are connected to the respective word lines WL
1
and WL
2
.
When the write operation is initiated, the high voltage charge pump
380
increases a supply voltage V
0
from a voltage source (not shown) so as to output a voltage V
1
of 10 V, for example. The voltage V
1
is decoded by the row decoder
320
into a voltage Vp of 10 V, for example, and output to the word line WL
0
. Whereas another voltage Vs of 0 V, for example, is output from the row decoder
320
to the word lines WL
1
and WL
2
. Each of these voltages are applied to the control gate
18
of the memory cell M which is connected to the respective word line WL, thereby controlling whether or not to perform a write operation to the memory cell M.
The operation of applying a voltage to the drain
14
b
of the memory cell M via the bit line BL will be described. The voltage V
1
from the high voltage charge pump
380
is regulated by a regulator circuit
1
to provide a stable voltage V
1
a (e.g., 6 V). Whether or not the voltage V
1
a
is to be applied to each bit line BL is controlled by the MOS transistors (Tr
01
and Tr
02
or Tr
11
and Tr
12
) which is connected to the bit line BL. The MOS transistors Tr
01
and Tr
11
are controlled by data which is externally provided via a node
1
and a node
2
, respectively. Whereas the MOS transistors Tr
02
and Tr
12
together form a column switch
344
and are commonly controlled by an externally provided control signal Vc.
At the initiation of a write operation, a node
0
is brought to a “high” level (e.g., the level of the voltage V
0
) and the node
1
is brought to a “low” level (e.g., the reference voltage of 0 V) by the externally provided data. The “high” level at the node
0
is latched by a latch circuit
342
a
and then level-converted by a level shift circuit HV
0
into a “high” level which corresponds to the level of the voltage Vp at a node H
0
. Thus, the MOS transistor Tr
01
is turned ON. On the other hand, the “low” level at the node
1
is latched by a latch circuit
342
b
and then level-converted by a level shift circuit HV
1
whose output is still at the “low” level (0 V). Thus, the MOS transistor Tr
11
is OFF.
The externally provided control signal Vc at the “high” level (the level o
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Tran M.
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