Semiconductor device

Details Semiconductor device Semiconductor device

1999-09-09

2002-05-07

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000, C438S637000

Reexamination Certificate

active

06384484

ABSTRACT:

TECHNICAL FIELD
The present invention relates a wiring forming method for a semiconductor device and a semiconductor device of forming wirings made of a metal material in connection holes or wiring grooves formed on a semiconductor substrate for conducting connections between wirings and semiconductor substrates and, more in particular, it enables complete and uniform filling of the metal material into connection holes or wiring grooves without complicating a production process.
BACKGROUND ART
Wirings in integrated circuits such as LSIs have been generally formed by fabricating films of aluminum (Al) series alloys deposited by a sputtering method by using, for example, photolithography or dry etching.
However, along with increasing degree of integration in semiconductor integrated circuits, diameters for connection holes or diameters for wiring grooves apertured for conducting connection between wirings and semiconductor substrates have become finer and an aspect ratio of them has been increased more and more. Therefore, it is difficult to form wirings at a predetermined thickness as far as the inside of the connection holes by the sputtering method to result in a problem of lowering the step coverage, increasing the resistance of contact hole wirings and deteriorating electro-migration durability.
In order to avoid them, a method of forming wirings to a vertical wiring portion in connection holes by a CVD method (chemical vapor deposition method) using tungsten (W) is adopted in LSIs under a design rule below half-micron.
However, in the existent method of forming wirings by the CVD method using tungsten, since the resistance of tungsten is high, it is necessary to leave a tungsten film formed on the entire surface of a substrate only in the connection holes while removing other portions by a dry etching method or chemical and mechanical polishing method (CMP) and form wirings of an aluminum series alloy again. Therefore, this gives rise to a problem of making the wiring forming step lengthy to increase the cost.
On the other hand, as the size for the wirings has become finer, it has been desired for wiring materials of high electro-migration durability and low resistance, and a film deposition method and a wiring fabrication method have now been under study for using copper capable of satisfying such a demand for the wiring material.
However, since a film of copper can not be deposited uniformly in a connection hole by a usual sputtering method, a method of depositing the copper film by a CVD method has been studied, but it still leaves a subject such as for the development of organic metal compounds of copper as a starting material and the development for CVD apparatus.
Further, while an electrolytic plating method for copper has also been studied, electrodeposition proceeds at the periphery outside of the fine connection holes or wiring grooves to at first close inlets for the connection holes or wiring grooves, which causes a problem of difficulty for filing copper in the fine connection holes without forming voids.
Further, it is difficult to fabricate copper by dry etching and it has been proposed, for example, a DUALDER machine method of forming contact holes and wiring grooves to an insulation film, depositing copper for the entire surface and then removing excess copper by a chemical and mechanical polishing method thereby properly forming wirings having vertical connection portions. Development for the technique of properly filling and depositing a copper film into hole or groove portions of high aspect ratio such as connection hole or wiring grooves has also been desired with an aim of applying to this method.
In view of the above, the present invention has been accomplished taking notice of the foregoing not yet solved subject and it is an object thereof to provide a selective plating method capable of completely, and uniformly filling groove or hole portions of high aspect ratio and a wiring forming method for a semiconductor device using the same, as well as a semiconductor device using the method.
DISCLOSURE OF THE INVENTION
In order to attain the foregoing object, the present invention provides a method of forming wirings for a semiconductor device, which comprises the steps of forming concaved wiring channels in an insulation film deposited on a semiconductor substrate, forming a first conductor layer having a first deposition overvoltage as a deposition overvoltage required for depositing a copper series metal material in a plating solution at a predetermined rate to the surface of the insulation film including the inner surface of the concaved portion of the wiring channels, then forming thereon a second conductor layer having a second deposition overvoltage higher than the first deposition overvoltage as the deposition overvoltage so as to cover a region except for the inner surface of the concaved portion of the wiring channels, subsequently, dipping at least the inner surface of the concaved portion of the wiring channels into the plating solution and applying a plating treatment at a deposition overvoltage higher than the first deposition overvoltage and lower than the second deposition overvoltage to deposit the copper series metal material, and polishing the deposited metal material thereby forming wirings.
That is, the first conductor layer having the first deposition overvoltage as the deposition overvoltage is formed to a region including the inner surface of the concaved portion of the wiring channels such as connection holes or wiring grooves formed in the concaved shape to the insulation film deposited on the semiconductor substrate, for example, by a CVD method, and then the second conductor layer having the second deposition overvoltage as the deposition overvoltage is formed there on so as to cover the surface of the insulation film except for the inner surface of the concaved portion of the wiring channels, for example, by a sputtering method. Then, they are dipped in the plating solution such that at least the entire surface of the inner surface of the concaved portion of the wiring channels is dipped in the plating solution, and plating is applied at a deposition overvoltage higher than the first deposition overvoltage and lower than the second deposition overvoltage. Since the deposition overvoltage is a voltage required for depositing the copper series metal material in the plating solution at a predetermined rate, the metal material is not deposited on a portion in which the second conductor layer is exposed, whereas chemical reactions are taken place between the metal material in the plating solution and the first conductor layer to deposit the metal material and apply copper plating to the portion in which the first conductor layer is exposed. That is, since copper plating is applied only to the portion in which the first conductor layer is exposed, namely, only to the inside of the concaved portion of the wiring channels intended to be applied with plating, to result in a copper-filled state, a wiring consisting of copper filled in the wiring channels can be obtained by polishing the copper.
In this case, the second conductor layer is preferably formed by a highly anisotropic deposition method. This is done for forming the second conductor layer to a region except for a region to be plated, namely, only to a region except for the wiring channels and the formation of the second conductor layer to the wiring channels can be avoided.
Further, it is preferred that each wiring channel has an aspect ratio of 1 or greater and 5 or less and a width of 1.0 &mgr;m or less. This is so defined for avoiding the formation of the second conductor layer at the bottom of the wiring channels upon forming the second conductor layer, for example, by a sputtering method.
Further, in a case of applying to a semiconductor device of a multi-layered wiring structure, plating is applied to form wirings and then wirings are conducted by forming a metal film further thereon. When wirings are formed on an insulator, a thin electrically conductive film is genera

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