Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2001-10-04

2002-09-24

Le, Vu A. (Department: 2819)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110

Reexamination Certificate

active

06456559

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor integrated circuits and more particularly to a semiconductor integrated circuit having a plurality of inputs such as a decoder circuit of a semiconductor memory.
BACKGROUND OF THE INVENTION
In order to reduce the size of a semiconductor device, such as a dynamic random access memory (DRAM), component density has continued to increase. As the circuit and wiring miniaturization has increased, the demand for lower power consumption has increased. One method of decreasing power consumption has been to decrease the internal power supply voltage used by the on-chip circuitry.
In general, when the power supply voltage is decreased, gate delay time (tpd) increases which decreases the device operation speed. In order to minimize the gate delay time, the threshold voltage of transistors such as metal oxide semiconductor field effect transistors (MOSFET) can be decreased. This can have the affect of increasing transconductance (gm) so the drive strength can be improved. However, when the threshold voltage is made small, sub-threshold current increases which can cause an increase in standby current and power consumption.
An approach directed to improve the sub-threshold current problem has been disclosed in Japanese Patent Laid-Open No. 6-208790 (JP 6-208790) and will be explained with reference to FIG.
9
. Referring now to
FIG. 9
, a circuit schematic diagram illustrating a conventional string of inverters is set forth. Each inverter is configured as a CMOS (complementary metal oxide semiconductor) inverter in which there is a n-type MOSFET and a p-type MOSFET. For example, the initial stage inverter is made up of n-type MOSFET Q
1
and p-type MOSFET Q
3
. The subsequent stage inverter is made up of n-type MOSFET Q
2
and p-type MOSFET Q
4
.
In the string of inverters illustrate in
FIG. 9
, the threshold voltage of the transistors that are to be turned off during standby have been increased and are larger than the threshold voltage of the transistors that are turned on in standby. In this example, when the semiconductor device is in standby, a logic low is input into the initial stage inverter (Q
1
and Q
3
). In this state, n-type MOSFET Q
1
and p-type MOSFET Q
4
are turned off. Accordingly, n-type MOSFET Q
1
has a threshold voltage VT
1
that is set higher than the threshold voltage VT
2
of n-type MOSFET Q
2
. Likewise, p-type MOSFET Q
4
has a threshold voltage VT
4
that is higher than the threshold voltage VT
3
of p-type MOSFET Q
3
.
In this way, when the input signal of the initial stage inverter (Q
1
and Q
3
) is low, the string of inverters is in the standby state. In this standby state, n-type MOSFET Q
1
and p-type MOSFET Q
4
are turned off while n-type MOSFET Q
2
and p-type MOSFET Q
3
are turned on. With p-type transistor Q
3
turned on, a low impedance path is created through p-type transistor Q
3
to the power supply. However, because n-type MOSFET Q
1
has a high threshold voltage VT
1
, the sub-threshold leakage current is reduced. Thus, the current leaking from the power supply to ground is reduced in the standby state. Because the output of the initial stage inverter (Q
1
and Q
3
) is logic high, n-type MOSFET Q
2
is turned on and p-type MOSFET Q
4
is turned off. With n-type transistor Q
2
turned on, a low impedance path is created through n-type transistor Q
2
to the ground potential. However, because p-type MOSFET Q
4
has a high threshold voltage VT
4
, the sub-threshold leakage current is reduced. Thus, the current leaking from the power supply to ground is reduced in the standby state.
However, the approach described in JP 6-208790 can have drawbacks. For example, in the case of a circuit system in which one logic gate drives a plurality of logic gates the gate delay time (tpd) and the stand-by current may not be effectively improved. One such example can be illustrated by considering a decoder of a semiconductor memory.
First, reasons why the gate delay time (tpd) may not be improved will be described.
Referring now to FIG.
10
(
a
), a circuit schematic diagram of a conventional decoder used in a semiconductor memory device is set forth.
The decoder of FIG.
10
(
a
) uses the approach set forth in JP 6-208790. In this case, when the decoder is in the standby state, transistors that are turned off have a high threshold voltage. As illustrated in
FIG. 10
, inverter
510
is a driver circuit used to drive a block selection line
520
. Inverter
530
is a driver circuit used to drive main word line
540
. Block selection line
520
and main word line
540
are used to select logic circuit
550
. Logic circuit
550
is used to drive a sub-word line. There are a plurality of block selection lines
520
and main word lines
540
disposed perpendicular to each other. A logic circuit
550
is disposed at intersecting points of a main word line
540
and block selection line
520
.
Block selection line
520
is connected to a plurality of logic circuits
550
in the column direction. Thus, inverter
510
is configured to drive the plurality of logic circuits
550
. Additionally, main word line
540
is connected to a plurality of logic circuits
550
in the row direction. Likewise, inverter
530
is configured to drive the plurality of logic circuits
550
.
Inverters (
510
and
530
) each drive a plurality of logic circuits
550
, however, only the logic circuit
550
that receives a high logic level from block selection line
520
and main word line
540
is selected. Logic circuits
550
that receive a low logic level from either block selection line
520
or main word line
540
are in a non-selection state.
Logic circuit
550
consists of a NAND gate
551
and an inverter
552
that are together configured to produce a logical AND output of the signals received on the block selection line
520
and main word line
540
. NAND gate
551
receives block selection line
520
and main word line
540
and produces an output that is received as an input of inverter
552
. Inverter
552
produces an output that is a sub-word line signal.
Referring now to FIG.
10
(
b
), a circuit schematic diagram of NAND
551
is set forth. NAND
551
is a CMOS NAND gate that has p-type MOSFETs (
5511
and
5512
) and n-type MOSFETs (
5513
and
5514
). P-type MOSFET
5511
has a source connected to a power supply, a drain connected to an output, and a gate connected to block selection line
520
. P-type MOSFET
5512
has a source connected to a power supply, a drain connected to an output, and a gate connected to main word line
540
. N-type MOSFET
5513
has a source connected to a drain of n-type MOSFET
5514
, a drain connected to the output and a gate connected to block selection line
5513
. N-type MOSFET
5514
has a source connected to ground and a gate connected to main word line
540
.
In the conventional decoder as illustrated in
FIG. 10
, p-type MOSFET
5511
and n-type MOSFET
5513
will be switched in a complementary fashion in accordance with the signal level on block selection line
520
. Likewise, p-type MOSFET
5512
and n-type MOSFET
5514
will be switched in a complementary fashion in accordance with the signal level on main word line
540
.
The gate capacitance of a MOSFET is significantly larger when the MOSFET is turned on than when it is turned off. Block selection line
520
is connected to a plurality of logic circuits
550
. Because block selection line
520
is connected to a p-type MOSFET
5511
and a n-type MOSFET
5513
, there is always a MOSFET that is turned on. When block selection line
520
is low, p-type MOSFET
5511
is turned on and has increased capacitance. When block selection line
520
is high, n-type MOSFET
5513
is turned on and has increased capacitance. Thus, the capacitive load on block selection line
520
is always relatively large. This can increase the gate delay time of inverter
520
and can affect the overall circuit operating speed.
Additionally, when the threshold voltage of a MOSFET is decreased to compensate for a decreased power supply pot

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