Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1998-12-16
2002-01-08
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C327S564000, C341S144000
Reexamination Certificate
active
06338032
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of integrated circuit (IC) parameter trimming techniques.
2. Description of the Related Art
Many integrated circuits, particularly analog ICs such as voltage references and operational amplifiers, have parameters which must be “trimmed” to deliver the performance promised in the IC's specifications. IC op amps, for example, often include trim inputs for adjusting an amplifier's offset voltage, which is varied in accordance with an applied trim signal.
A number of techniques are employed to achieve the specified performance. For example, a number of wafers can be tested, with those that meet the specifications kept and the others rejected. Since this approach requires each wafer to be tested, yet results in a number of wafers being discarded, it is very costly. Another common technique involves the use of thin film resistors that are laser trimmed during assembly. This method requires the use of costly equipment, the use of which is very time consuming. Furthermore, because the trimming is done during assembly, the trimmed parameter may drift due to subsequent assembly steps.
Another disadvantage to conventional trimming techniques arises when a parameter needing trimming is not accessible via one of the IC's I/O pins, i.e., the value of the parameter cannot be determined by connection to any I/O pin. To enable these otherwise inaccessible parameters to be measured, probe pads are located on the wafer. However, the probe pads, with a typical size of 100 &mgr;m×100 &mgr;m each, occupy considerable space and thereby increase die cost.
A trimming approach specifically directed to providing a trimmed resistance value is described in U.S. Pat. No. 5,361,001 to Stolfa. Rather than laser trim a thin film resistor, Stolfa uses a resistive ladder network. Some of the ladder's individual resistors have respective transistors connected across them, which, when switched on, disable conduction through the resistor and effectively remove it from the ladder network. Stolfa's method allows a proposed trim value to be “previewed”, and if found acceptable, fuses can be blown to permanently fix the configuration of the ladder network.
Stolfa's method suffers from several serious drawbacks, however. Each of his transistors is operated with a respective control circuit, each of which receives an input via a respective pin on the IC package. The number of IC pins required for this parallel input of data may be unacceptably large. Also, his data input and fuse blowing circuitry is very simple, with nothing provided to prevent the accidental (permanent) trimming of the ladder to an erroneous value. Stolfa's method in apparently intended for adjusting a single parameter, and no means of measuring parameters not accessible via an I/O pin is provided. Furthermore, Stolfa removes resistors from the ladder network by switching on a transistor that is connected across the resistor. Because the resistance through a transistor can vary over time and temperature, the trimmed value is susceptible to drift.
SUMMARY OF THE INVENTION
A system and method for trimming and simulating the effect of trimming IC parameters are presented which overcome the problems noted above. Trim values for a number of different parameters can be iteratively simulated until acceptable, and then accurately and permanently fixed.
The invention provides trim signals, i.e., currents and/or voltages, each of which affects a respective IC parameter such as the offset voltage of an operational amplifier. The trim signals are preferably generated with respective digital-to-analog converters (DACs) in response to digital bit patterns received at their respective inputs. During trim simulation, a data latch circuit receives a bit pattern via an input/output (I/O) pin, latches it, and applies it to a DAC associated within a particular parameter of interest. Bit patterns are iteratively applied until one is identified that brings the associated parameter within an acceptable range. The trim is then made permanent by activating an interface circuit to permanently encode the identified bit pattern so that it is always applied to the DAC's input.
The system preferably receives bit patterns in a serial bit stream via a single I/O pin, to reduce the number of pins needed by the system. To insure the validity of the incoming bit patterns and prevent accidental erroneous trimming, the system is arranged to require the receipt of specific data sequences before a trim signal will be simulated or the fuses blown. A number of DACs are provided to enable a number of different parameters to be simulated and trimmed. To allow internal IC nodes that are not connected to an I/O pin to be monitored during trim simulation, a switching network is provided that selectably switches the internal nodes to a specified I/O pin for measurement.
The circuitry being trimmed, along with the system's data latch, DAC, and interface circuits are all packaged within the same IC package. The simulation and trimming of the IC's parameters is preferably done post-assembly, eliminating the risk of post-assembly drift associated with prior art trimming techniques. The need for probe pads on a wafer is also eliminated.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.
REFERENCES:
patent: 5361001 (1994-11-01), Stolfa
patent: 5396130 (1995-03-01), Galbraith et al.
patent: 5760720 (1998-06-01), Nolan et al.
patent: 6107950 (2000-08-01), Fisher et al.
patent: 6118398 (2000-09-01), Fisher et al.
Tang et al., A.T.K. Self-Calibration for High Speed, High-Resolution D/A Converters, 2nd International Conference on Advanced A-D and D-A Conversion Techniqies and Their Applications, Jul. 1994, pp. 142-147.*
Conroy et al., C.S.G. Statistical Design Techiques for D/A Converters, IEEE Journal of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, pp. 1118-1128.*
Gu et al., Z. A Novel Self-Calibrating for Video-Rate 2-Step Flash Analog-to-Digital Converter, 1992 IEEE International Symposium on Circuits and Systems, ISCAS '93, vol. 2, pp. 601-604.*
Das et al., S. Electrical Trimming of Ion-Beam-Sputtered Polysilicon Resistors by High Current Pulses, IEEE Transactions on Electron Devices, vol. 41, No. 8, Aug. 1994, pp. 1429-1434.*
Suh et al., Jung-Won Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 1025-1028.*
Gupta et al., S. A 3 to 5 V CMOS Bandgap Voltage Reference with Novel Trimming, IEEE 39th Midwest Symposium on Circuits and Systems, vol. 2, Apr. 1996, pp. 969-972.*
Mijanovic et al., Z. R/2R/sup +/Digital-Analog Converter (DAC), Instrumentation and Measurement Technology Conference, Proceedings, Quality Measurements: The Indespensable Bridge between Theory and Reality, IEEE, vol. 2, Jun. 1996, pp. 1034-1039, Jul. 1994.
Analog Devices Inc.
Frejd Russell W.
Koppel & Jacobs
Teska Kevin J.
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