Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1998-08-28
2002-04-16
Banankhah, Majid A. (Department: 2151)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S229000
Reexamination Certificate
active
06374282
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to communication of information between nodes on a network and particular to tracking the status of independent transactions (multiple threads).
2. Description of the Relevant Art
One type of network is ServerNet developed by the assignee of the present application and described in detail in U.S. Pat. No. 5,675,807. ServerNet is an input/output (I/O) system area network system that provides redundant communication paths between various components of a large processing system, including a CPU and assorted peripheral devices (e.g., mass storage units, printers, and the like) of a sub-processing system, as well as between the sub-processors that may make up the larger overall processing system. Communication between any component of the processing system (e.g., a CPU and a another CPU, or a CPU and any peripheral device, regardless of which sub-processing system it may belong to) is implemented by forming and transmitting packetized messages that are routed from the transmitting or source component (e.g., a CPU) to a destination element (e.g., a peripheral device) by a system area network structure comprising a number of router elements that are interconnected by a bus structure (herein termed the “SNet”) of a plurality of interconnecting links. The router elements are responsible for choosing the proper or available communication paths from a transmitting component of the processing system to a destination component based upon information contained in the message packet. Thus, the routing capability of the router elements provide the I/O system of the CPUs with a communication path to peripherals, but permits it to also be used for interprocessor communications.
ServerNet implements a technique of validating access to the memory of any end node, e.g., a CPU node or I/O node. The processing system, as structured according to the present invention, permits the memory of any CPU to be accessed by any other element of the system (i.e., other CPUs and peripheral devices). This being so, some method of protecting against inadvertent and/or unauthorized access must be provided. In accordance with this aspect of the invention, each CPU maintains an access validation and translation (AVT) table containing entries for each source external to the CPU that is authorized access to the memory of that CPU. Each such AVT table entry includes information as to the type of access permitted (e.g., a write to memory), and where in memory that access is permitted. Message packets that are routed through the network are created, as indicated above, with information describing the originator of the message packet, the destination of the message packet, what the message contains (e.g., data to be written at the destination, or a request for data to be read from the destination), and the like. In addition to permitting the router elements to route the message packet to its ultimate destination expeditiously, the receiving CPU uses the information to access the AVT table for the entry pertaining to the source of the message packet, and check to see if access is permitted, and if so what type and where the receiving CPU chooses to remap (i.e., translate) the address. In this manner the memory of any CPU is protected against errant accesses. The AVT table is also used for passing through interrupts to the CPU.
The AVT table assures that a CPUs memory is not corrupted by faulty I/O devices. Access rights can be granted from memory ranging in size from 1 byte to a range of pages. This fault containment is especially important in I/O, because the vendors of systems usually have much less control over the quality of hardware and software of third-party peripheral suppliers. Problems can be isolated to a single I/O device or controller rather than the entire I/O system.
In ServerNet, a block transfer engine (BTE) is provided in each CPU to handle input/output information transfers between a CPU and any other component of the processor system. Thereby, the individual processor units of the CPU are removed from the more mundane tasks of getting information from memory and out onto the SNet network, or accepting information from the network. The processor unit of the CPU merely sets up data structures in memory containing the data to be sent, accompanied by such other information as the desired destination, the amount of data and, if a response is required, where in memory the response is to be placed when received. When the processor unit completes the task of creating the data structure, the block transfer engine is notified to cause it to take over, and initiate sending of the data, in the form of message packets. If a response is expected, the block transfer engine sets up the necessary structure for handling the response, including where in memory the response will go. When and if the response is received, it is routed to the expected memory location identified, and notifies the processor unit that the response was received.
When the processors set up the BTE data structure, a transaction number (TN) is assigned to the request by a request transaction protocol layer and is included in the header field of the message packet that will be formed and sent by the BTE. Each transaction is a request-response pair. The processors will also include an memory address in the BTE data structure at which the data, when received, is to be placed. When the BTE logic sends the packet on its way, the memory address of the buffer location is written to a register file in the request transaction logic, using the TSN as a pointer into the register file.
When the response is received by the CPU, the request transaction logic will use the transaction number (TN) from the header at which the data contained in the incoming message packet is to be placed in the memory.
The resources used to generate SeverNet transactions on a CPU node are single-threaded. The resources, a block transfer engine (BTE) and a transaction-layer protocol checker (TLP) can source multiple active transactions, but they are single-threaded; that is, they are all related to a common descriptor. A new descriptor cannot start until the current descriptor has completed. In addition, the TLP requires all transaction responses to transaction requests to be received in the same order as they were sent out. As networks are required to perform at higher speeds and provide more bandwidth, improvements to single-threaded designs with restrictive ordering constraints will be required.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a network protocol provides multi-threaded transaction processing by keeping track of the status of a plurality of independent outstanding requests.
According to another aspect of the invention, time-out data for multiple independent transactions is maintained by a transaction layer protocol (TLP). A time-out of a transaction is utilized to invalidate the transaction.
According to a further aspect, each transaction request is described by a descriptor which includes a unique transaction number (TN) identifying the request. When a request is received by the transaction layer protocol the unique transaction number is used to set an active transition bit indexed by the TN.
According to a further aspect, a time-out value, included in a request descriptor, is stored when a request is received by the TLP, with the time-out value indexed by the unique TN of the request. A time out process periodically decrements each stored time-out value to keep track of the time elapsed for each outstanding independent request.
According to another aspect of the invention, each independent request may have a different time-out value stored in its descriptor.
Only those storage locations corresponding to requests having active transaction bits set are accessed by a time-out process. A stored time value is read, decremented, and, if the decremented time value is not equal to a predetermined value, written back to the storage location indexed by th
Brown David A.
Bunton William P.
Banankhah Majid A.
Compaq Computer Corporation
Oppenheimer Wolff & Donnelly
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